Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same

A method of forming an array of electrically programmable and erasable memory devices, comprising:

• forming spaced apart isolation regions on a semiconductor substrate that are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, wherein the substrate has a surface and a first conductivity type;
• and
• forming a plurality of pairs of memory cells in each of the active regions, wherein the formation of each of the memory cell pairs includes:
• forming a trench into the surface of the substrate having a pair of opposing sidewalls,
• forming a first region in the substrate and underneath the trench,
• forming a pair of second regions in the substrate, with a pair of channel regions each defined in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, and wherein each of the channel regions includes a first portion that extends substantially along one of the opposing trench sidewalls and a second portion that extends substantially along the surface of the substrate,
• forming a pair of electrically conductive floating gates each having at least a lower portion thereof disposed in the trench adjacent to and insulated from one of the channel region first portions for controlling a conductivity of the one channel region first portion,
• forming a pair of electrically conductive erase gates each having at least a lower portion thereof disposed in the trench adjacent to and insulated from one of the floating gates;
• and
• forming a pair of electrically conductive control gates each disposed over and insulated from one of the channel region second portions for controlling a conductivity of the one channel region second portion.