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US 7,547,598 B2Granted
Method for fabricating capacitor in semiconductor device
AssigneeHynix Semiconductor Inc.
InventorHyung-Bok Choi
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AssigneeHynix Semiconductor Inc.
InventorHyung-Bok Choi
Estimating the term…
A method for fabricating a capacitor in a semiconductor device includes forming a first insulation layer over a substrate, forming storage node contact plugs in the first insulation layer, contacting predetermined portions of the substrate, forming a second insulation layer over the first insulation layer and the storage node contact plugs, forming trenches exposing the storage node contact plugs, forming storage nodes in the trenches, forming a plasma barrier layer over the second insulation layer and the storage nodes, forming a capping layer over the plasma barrier layer and filled in the trenches, removing the capping layer, the plasma barrier layer, and the second insulation layer, forming a dielectric layer over the storage nodes, and forming a plate electrode over the dielectric layer.
A method for fabricating a capacitor in a semiconductor device, the method comprising:
A method for fabricating a capacitor in a semiconductor device, the method comprising:
A method for fabricating a capacitor in a semiconductor device, the method comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Of capacitors having no potential barriers: using deposition processes to form electrode extensions
Manufacture or treatment: with simultaneous manufacture of the peripheral circuit region and memory cells
Having non-planar surfaces, e.g. formed by texturisation: having vertical extensions
Making the capacitor or connections thereto: the capacitor extending over the transistor
About Less than a month of term left · ends 7 Nov 2026 (estimated)
The present application is based upon and claims the benefit of priority to Korean patent application Nos. KR 2006-0002139 and KR 2006-0068467, filed in the Korean Patent Office on Jan. 9, 2006 and Jul. 21, 2006, respectively, the entire contents of which are incorporated herein by reference.
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a cylinder type capacitor in a semiconductor device.
As critical dimensions have decreased and the scale of integration has increased in a semiconductor memory device, an area on which a capacitor is formed has gradually become smaller.
The above and other features of the present invention will become better understood with respect to the following description of the specific embodiments given in conjunction with the accompanying drawings, in which:
FIGS. 1A to 1D are cross-sectional views illustrating a conventional method for fabricating a capacitor in a semiconductor device;
FIGS. 2A and 2B are micrographic views showing micro-bridges generated by the conventional method; and
A method for fabricating a capacitor in a semiconductor device consistent with the present invention will be described in detail with reference to the accompanying drawings.
FIGS. 3A to 3E are cross-sectional views illustrating a method for fabricating a capacitor in a semiconductor device consistent with the present invention.
As shown in FIG. 3A, a substrate 31 is defined into a cell region and a peripheral region, and a first inter-layer insulation layer 32 is formed over the substrate 31. Then, storage node contact plugs 33 are formed in the first inter-layer insulation layer 32 in the cell region, contacting predetermined portions of the substrate 31. Although not illustrated, transistors, word lines, or bit lines may be formed before the first inter-layer insulation layer 32 is formed. The first inter-layer insulation layer 32 may comprise one selected from a group consisting of a borosilicate glass (BSG) layer, a borophosphosilicate glass (BPSG) layer, a phosphosilicate glass (PSG) layer, a tetraethyl orthosilicate (TEOS) layer, a high density plasma (HDP) layer, a spin on glass (SOG) layer, and an advanced planarization layer (APL). The inter-layer insulation layer may also have a multi-layer structure including an organic-based or inorganic-based low-k dielectric layer.