Method of enhancing drive current in a transistor

#The invention is directed, in general, to forming MOS transistors, and, more specifically, to increasing the drive current of the transistors.

#Semiconductor devices, such as transistors, have reached well into the sub-micron range, e.g., below 0.25 microns. The semiconductor manufacturing industry has made continued advances in overall device speed and performance, while continually shrinking device size and increasing component density.

#Creating strain in channel regions of planar MOS transistors may increase the mobility of charge carriers in the channel region. So-called “strain engineering” seeks to take advantage of this principle to increase the switching speed of the transistors. In general, tensile strain increases the mobility of electrons, while compressive strain increases the mobility of holes.

#For a more complete understanding of the invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

#FIGS. 1-10 illustrates MOS transistors at various stages of completion; and

#FIG. 11 illustrates a semiconductor device.

#One method that has been used to engineer the strain of n-channels and p-channels is the deposition of a stressed dielectric film such as silicon nitride over the transistors. The stress in the film is transferred to the channel region to produce the desired compressive or tensile strain in the channel. However, the magnitude of the strain that may be induced in the channel region is limited.

#The gate electrode of a MOS transistor is typically exposed during the implantation of dopants into the source/drain regions. Implanting the source/drain dopant into the gate electrode generally increases the proportion of amorphous material in the gate electrode. This proportion is referred to herein as the “amorphous content” of the gate electrode.

#When a gate electrode with amorphous content is annealed in a thermal process, the volume of the gate electrode generally decreases as the amorphous material crystallizes. If a dielectric capping layer is formed over the gate electrode before the annealing, the reduction of volume may result in stress in the gate region that produces lattice strain.