Metal-oxide-semiconductor transistor and method of forming the same
AssigneeUnited Microelectronics Corp.
InventorChin-Sheng Yang
Life of this patent
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Abstract
A method of forming a metal-oxide-semiconductor (MOS) transistor device is provided. First, a semiconductor substrate is prepared. Subsequently, a gate structure is formed on the semiconductor substrate. The gate structure includes a first strip portion and a second strip portion that is not parallel to the first strip portion. The gate structure further includes a junction between the first strip portion and the second strip portion. Thereafter, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure. Next, a portion of the stressed cap layer is removed to expose the junction between the first strip portion and the second strip portion.
Claims17
A method of forming a metal-oxide-semiconductor (MOS) transistor, comprising:
- providing a semiconductor substrate;
- forming a gate structure on the semiconductor substrate, the gate structure comprising a first strip portion and a second strip portion that is not parallel to the first strip portion, the gate structure further comprising a junction between the first strip portion and the second strip portion;
- forming a stressed cap layer on the semiconductor substrate, covering the gate structure;
- and
- removing a portion of the stressed cap layer to expose a portion of the semiconductor substrate, and the junction between the first strip portion and the second strip portion without punching through the gate structure.
A MOS transistor, comprising:
- a semiconductor substrate;
- a gate structure disposed on the semiconductor substrate, comprising a first strip portion and a second strip portion that is not parallel to the first strip portion, further comprising a junction between the first strip portion and the second strip portion;
- a source region disposed in the semiconductor substrate;
- a drain region disposed in the semiconductor substrate;
- a channel region disposed in the semiconductor substrate under the gate structure between the source region and the drain region;
- and
- a stressed cap layer covering the gate structure, the source region, and the drain region, and exposing the junction and a re-entrant between the first strip portion and the second strip portion.
Dependencies are inferred from the claim text.