PMOS depletable drain extension made from NMOS dual depletable drain extensions

#The subject matter of this application relates to transistors. More particularly, the subject matter of this application relates to PMOS and NMOS devices with depletable drain extensions.

#Conventional structures used to build high voltage MOS devices, such as PMOS device 100 shown in FIG. 1, include a P drain extension 110 that extends from the drain edge of the gate 112 to a P+ drain contact 120. The P drain extension 110 is designed so that under reverse drain to body bias, the drain extension 110 totally depletes before breakdown occurs at the drain extension to body junction under the edge of the gate 112. In this design, the P+ drain contact 120 is separated from the high field induced by the gate 112, which is also separated from the drain body junction by a thin gate oxide 130. This makes it possible for the PMOS device 100 to achieve a higher breakdown voltage.

#Some applications, however, call for both high voltage NMOS and high voltage PMOS devices on the same structure. One conventional approach has been to make the NMOS using a quasi-vertical diffused metal-oxide semiconductor device (DMOS). A quasi-vertical DMOS device, however, requires a heavy doped buried layer, a sinker, and a thick epitaxial layer with closely controlled resistivity and thickness. These structures increase the complexity and cost of processing.

#FIG. 1 is schematic diagram of a conventional PMOS device with a drain extension;

#FIG. 2 is a schematic diagram of an N DMOS device of an integrated circuit device having a drain extension region according to various embodiments of the present invention;

#FIG. 3 is a schematic diagram of a PMOS device of an integrated circuit device having a drain extension region according to various embodiments of the present invention;

#In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific exemplary embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the invention. The following description is, therefore, not to be taken in a limited sense.

#Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, all ranges disclosed herein are to be understood to encompass any and all sub-ranges subsumed therein. For example, a range of “less than 10” can include any and all sub-ranges between (and including) the minimum value of zero and the maximum value of 10, that is, any and all sub-ranges having a minimum value of equal to or greater than zero and a maximum value of equal to or less than 10, e.g., 1 to 5.

#FIGS. 2-5 depict exemplary methods and devices for use in forming complementary drain extended MOS devices. According to various embodiments, a dual drain extension device, such as that illustrated in FIG. 2 can be used for one type of device (for example an NMOS) and a single drain extension device can be used for the second, complementary type of device (for example a PMOS). Other examples of dual depleteable drain extension devices are described in U.S. Pat. Nos. 4,823,173; 5,338,960; and 5,264,719, which are incorporated by reference in their entirety herein.