US 7,547,590 B2 · Method for forming an array substrate including forming a transparent conductive layer on a photoresist and laser ablating

Abstract

Disclosed is a method for manufacturing an array substrate utilizing a laser ablation process. With the laser ablation process, a photoresist layer is removed along with the transparent conductive layer therefrom, while maintaining other portions of the transparent conductive layer. Moreover, the laser ablation process of the invention does not need additional photo-mask, so the fabrication cost can be reduced.

Drawings

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Drawings

Claims16

Dependent claims

A method for manufacturing an array substrate, comprising:

providing a substrate;
forming a contact pad, a thin film transistor (TFT), a pixel region, and a storage capacitor on the substrate;
forming a passivation layer on the contact pad, the TFT, the pixel region, and the storage capacitor;
forming a patterned photoresist layer on the passivation layer;
removing part of the passivation layer uncovered by the patterned photoresist layer to expose the pixel region, part of the TFT, part of the storage capacitor, and part of the contact pad;
forming a transparent conductive layer on the patterned photoresist layer, on the exposed pixel region, on the exposed part of the TFT, on the exposed part of the storage capacitor, and on the exposed part of the contact pad;
and
applying a laser ablation process to remove the patterned photoresist layer and the transparent conductive layer on the patterned photoresist layer, so that the transparent conductive layer remains on the pixel region, on the part of the TFT, on the part of the storage capacitor, and on the part of the contact pad.

5 more elements

Dependencies are inferred from the claim text.

Description3,619 words

Summary624 words

#1. Field of the Invention

#The present invention relates to a method for forming an array substrate and, most particularly, to use of a laser ablation process to manufacture the array substrate.

#2. Description of the Related Art

Brief description of the drawings4 figures

#The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention.

#FIGS. 1A-1E are serial cross-sectional views of processes in conventional TFT array substrate fabrication;

#FIG. 2A is a top-view of an array substrate of an embodiment of the present invention, FIGS. 2B-2E are serial cross-sectional views of a method of the embodiment of the present invention along the A-A line of FIG. 2A;

Detailed description2,872 words

#A detailed description is given in the following embodiments with reference to the accompanying drawings.

#The following description is of the best-contemplated mode of carrying out the present invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the present invention is best determined by reference to the appended claims.

#FIG. 2A is a top-view of an array substrate of an embodiment of the present invention. Gate lines 21 crosses data lines 22 to form the pixel region V with at least one TFT IV to control an orientation of the liquid crystal molecules. The terminals of the gate lines 21 and data lines 22 are contact pads III, and a top electrode 27B is formed overlying part of the gate lines 21 to form a storage capacitor VI. While one TFT is charted in FIG. 2A, pixel region V may contain more than one TFT or other kind of TFT such as storage capacitor controlling TFT, current flow controlling TFT, other TFT, or combination thereof. Furthermore, while the storage capacitor VI utilizes part of the gate lines 21 as bottom electrode, those skilled in the art will appreciate that the storage capacitor VI may utilize other gate lines such as common electrode (not shown) as bottom electrode.

Facts

Application

11/744,934Filed 7 May 2007

Priority

TW 95124150 A3 Jul 2006

Published

US 2008/0044953 A121 Feb 2008

Granted

16 Jun 2009

Term ends

4 Feb 2028

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 273 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification6 codes

H10D 86/0231
Of multiple TFTs: using masks, e.g. half-tone masks
H10D 86/481
Characterised by multiple TFTs: integrated with passive devices, e.g. auxiliary capacitors
H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
Y10S 438/951
Radiation resist: lift-off

Timeline

3 Jul 2006Priority claimedTW 95124150 A
7 May 2007Application filedUS 11/744,934
7 May 2007Assigned to Au Optronics Corp.assignment of assignor's interest
21 Feb 2008PublishedUS 2008/0044953 A1
16 Jun 2009GrantedUS 7,547,590 B2
12 Oct 2026TodayWithin its term
4 Feb 2028Term endsEstimated, includes 273 days of adjustment

Method for forming an array substrate including forming a transparent conductive layer on a photoresist and laser ablating

Life of this patent

Method for forming an array substrate including forming a transparent conductive layer on a photoresist and laser ablating

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims16

Description3,619 words

Drawings

Classification6 codes

Life of this patent

Description3,619 words