US 7,547,584 B2 · Method of reducing charging damage to integrated circuits during semiconductor manufacturing

Abstract

An integrated circuit die includes thereon a first device region, a second device region and a non-active region. A first implant mask, which covers the second device region and the non-active region, while exposing the first device region, is formed over the semiconductor substrate. Dopant species are implanted into the exposed semiconductor substrate within the first device region to form first doping regions therein. A second implant mask is formed over the semiconductor substrate. The second implant mask covers the first device region, while exposing the second device region and a portion of the non-active region. Dopant species are implanted into the exposed semiconductor substrate within the second device region to form second doping regions therein.

Drawings

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Drawings

Claims6

Dependent claims

A method for reducing charging damage to integrated circuits during semiconductor manufacturing, comprising:

providing a semiconductor substrate comprising thereon a number of integrated circuit dies, said integrated circuit dies being separated from each other by scribe lanes surrounding each said integrated circuit die, wherein said semiconductor substrate comprises thereon a dielectric layer;
forming a mask over said dielectric layer, said mask comprising an interconnect opening and a dummy, non-interconnect opening, wherein said interconnect opening and said dummy, non-interconnect opening both are formed within each said integrated circuit die;
performing a plasma etching process to etch said dielectric layer through said interconnect opening and said dummy, non-interconnect openings of said mask, thereby forming an interconnect recessed trench and a dummy recessed trench in said dielectric layer;
and
filling said interconnect recessed trench and said dummy recessed trench with conductive materials to form an interconnect feature and a dummy, non-interconnect feature, wherein said interconnect feature electrically connects to an underlying conductive layer, while said dummy, non-interconnect feature is floating or grounded to said semiconductor substrate;
wherein said dummy, non-interconnect opening increases an in-die shunt path current flow during said plasma etching process, thereby reducing charge damage to said integrated circuit dies.

3 more elements

Dependencies are inferred from the claim text.

Description3,947 words

Summary928 words

#1. Field of the Invention

#The present invention relates generally to the field of semiconductor fabrication and, more particularly, to a method of reducing charging damage to integrated circuits during semiconductor manufacturing. The present invention is particularly suited for ion implant processing in an ion implanter without employing a plasma flood system.

#2. Description of the Prior Art

Brief description of the drawings6 figures

#The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

#FIG. 1 is a schematic plan view of layout of a photoresist implant mask for implementing lightly doped drain (LDD) regions of high-voltage devices in an integrated circuit die;

#FIG. 2 is a schematic plan view of layout of a photoresist implant mask for implementing LDD regions of high-voltage devices in an integrated circuit die according to one preferred embodiment of the present invention;

Detailed description2,832 words

#In describing the preferred embodiment of the present invention, reference will be made herein to FIGS. 1-2 of the drawings. Features of the invention are not drawn to scale in the drawings.

#As previously described, high-current ion implanters are typically equipped with a plasma flood gun, which is an effective apparatus for suppressing positive charging of wafer. In some cases, however, the ion implanter is not equipped or operated with such plasma flood gun, for example, a medium-current ion implanter that is generally used to provide a dosage of about 1E11˜1E14 atoms/cm2 and ion implant energy of about 10 KeV˜500 KeV. Such medium-current ion implanters are typically employed to form lightly doped source/drain doping regions in the substrate.

#FIG. 1 is a schematic plan view of layout of a photoresist implant mask 20 for implementing lightly doped drain (LDD) regions of high-voltage devices in an integrated circuit die. As shown in FIG. 1, the integrated circuit die 10 is surrounded with scribe lanes 12. A number of test key regions (not explicitly shown) are defined within the scribe lanes 12. Within the integrated circuit die 10, device ion wells, gate oxide layer, polysilicon gates, and shallow trench isolation (STI) region have been formed on the substrate such as a silicon substrate.

Facts

Application

11/560,831Filed 16 Nov 2006 · continuation in part

Priority

27 May 2005

Published

US 2007/0093057 A126 Apr 2007

Granted

16 Jun 2009

Term ended

24 Oct 2025

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 150 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification12 codes

H10P 30/22
Into semiconductor materials, e.g. for doping: using masks
H10D 84/013
The components including insulated gates, e.g. IGFETs: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/0151
The components including insulated gates, e.g. IGFETs: manufacturing their isolation regions
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

Family

Application10/908,815Parent of this continuation-in-part · filed 27 May 2005

US 2007/0093057 A1Pre-grant publication · published 26 Apr 2007

US 7,176,051 B2Parent of this continuation-in-part

US 2006/0270161 A1Published application

US 7,547,584 B2This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

27 May 2005Priority claimedParent application 10/908,815
16 Nov 2006Application filedUS 11/560,831
16 Nov 2006Assigned to United Microelectronics Corp.assignment of assignor's interest
26 Apr 2007PublishedUS 2007/0093057 A1
16 Jun 2009GrantedUS 7,547,584 B2
26 Jul 2021Assigned to Marlin Semiconductor Limitedassignment of assignor's interest
24 Oct 2025Term endedEstimated, includes 150 days of adjustment

Method of reducing charging damage to integrated circuits during semiconductor manufacturing

Life of this patent

Method of reducing charging damage to integrated circuits during semiconductor manufacturing

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims6

Description3,947 words

Drawings

Classification12 codes

Life of this patent

Description3,947 words