Method of fabricating a surface adapting cap with integral adapting material for single and multi chip assemblies

#The present invention relates to an improved surface adapting cap with an integrated adapting thermally conductive material on one or more semiconductor chips in single and multi chip modules.

#The present invention is related to semiconductor device manufacturing technology, and in particular to the integrated circuit (IC) packaging. Semiconductor device manufacturing technology is continually being pushed to higher levels of density and speed, with the objective of offering ever increasing functionality in a single package. This trend is resulting in sharply increasing power densities that demand continuous improvements in cooling efficiency. The introduction of multichip modules has intensified the need for efficient cooling even further by creating a more complex thermal environment. The Controlled Collapse Chip Connection (C4) protocol has emerged as the dominant assembly process for semiconductor chips in the Single Chip Module (SCM) and multichip Module (MCM) assembly process. In this assembly process each chip is inverted (or “flipped”) and bonded both electrically and mechanically at each connecting interface to conductive elements on a supporting substrate. In this arrangement, the cooling mechanism is attached to the exposed upper surface (or “bottom”) of each chip through a thermal interface. The primary factor in determining the efficiency of the cooling mechanism is the effectiveness of this thermal interface resistance. A reduction in thermal interface resistance produces a significant improvement in the overall thermal performance.

#The thermal interface material comprises thermally conductive material (such as grease, adhesive, solder etc) that thermally connects the chip to the enclosing cap or sealing structure of the module. For optimal results it is necessary that the thickness of this interface material be regulated within the range of 100 μm to 10 μm. Current technological improvements suggest future trends to even lower distances of a few μm. The gap thickness is partially determined by the tolerances of the production process that range from about 60 μm to 12 μm dependent on the packaging system. This tolerance is caused by warpage of the chip, as well as position and angular tolerances in the placement of each chip. The trend towards ever reducing interface material thickness greatly enhances the significance of these variations.

#The present invention is described with the help of accompanying drawings:

#FIG. 1 shows the typical deviations from co-planarity in multi chip module (MCM).

#FIG. 2 shows the trend of thermal interface resistance and interface thickness.

#An embodiment of the present invention provides an adaptive material integral to the cap that adapts to the warping and placement tolerances of the chip. This may be better understood with the aid of the FIG. 1, which shows typical tolerances in multi chip module packing. In this z-offset 101, cap bow 102, chip bow 103, and angle tolerance 104 are shown, where multiple chips are mounted onto a common substrate and covered with a cap. On the bottom side of the cap is a thermally conductive material integrated which adjusts for the non-uniformity between cap and chip and defines a constant and equal gap between chip and cap. This gap then gets filled with a compliant thermal interface material such as paste, gel or adhesive.

#FIG. 2, illustrates the variation in thermal resistance as a function of interface thickness for different paste materials with the arrow showing the current trend towards smaller and smaller gaps. The ratio between the gap thickness and the thermal resistance is related to the bulk conductivity of the material. Materials on the lower right have high bulk conductivity while materials on the upper left have low bulk conductivity. FIG. 3 shows a previously-proposed method used to adapt to the surface of the chip, where non-planarity of the cap 306 is allowed up to about 12 μm and when the bowing of the chip 307 is 10 μm and a solder foil 302 and a membrane foil 304 are positioned between cap 303 and chip 301. The parts are precompressed with a force F. at assembly temperatures above the liquidus temperature of the solder foil 302. Below the liquidus temperature the solder foil 302 stores the warping of the chip 301. The membrane foil 303 is then removed and the thermal interface material is applied and compressed. This approach requires a highly viscous and thermally conductive and adaptive material 302 in combination with a fast assembly speed. Otherwise the pressure built-up during the squeezing is too low to deflect the membrane 304 properly and the material is just squeezed out at location 305 beyond an edge of the chip. Since materials like solder 302 are very low in viscosity above their liquidus temperature, this principle does not work satisfactorily, especially in case of concave warping.

#Due to this reason the above-described method includes the confinement of the adaptive material. This confinement allows the use of low viscous materials and allows reworkability. Another drawback of the method is the limited z-position tolerance due to the confinement of the adaptive material. In an embodiment of the present invention, the z-position tolerances are taken into account.