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AssigneesUnited Microelectronics Corp., AltaSens, Inc.
InventorsTzeng-Fei Wen, Giuseppe Rossi, Ju-Hsin Yen, Chia-Huei Lin, Jhy-Jyi Sze, Chien-Yao Huang, Teng-Yuan Ko, Nien-Tsu Peng
Estimating the term…
An image sensor and a method of manufacturing the same, in which, a planarized layer is formed on a semiconductor substrate including a pixel array region, an optical black region, and a logic region to cover a photo sensing unit array in the pixel array region, a patterned metal layer is formed on the planarized layer corresponding to the pixel array region and the logic region, but not the optical black region. An optical black layer is formed in the optical black region after a passivation layer is formed and before a color filter array is formed at a temperature less than about 400° C., and preferably contains metal material.
A method of manufacturing an image sensor device, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Coatings: optical shielding
Manufacture or treatment of image sensors covered by group H10F39/12: wafer-level processing
Constructional details of image sensors: of hybrid image sensors
Manufacture or treatment of image sensors covered by group H10F39/12: of CMOS image sensors
About 3 months of term left · ends 28 Jan 2027 (estimated)
1. Field of the Invention
The present invention relates to an image sensor and a method of manufacturing the same, and more particularly to, a CMOS image sensor and a method of manufacturing the same.
2. Description of the Prior Art
FIG. 1 is a cross-sectional diagram showing a conventional CMOS image sensor.
FIG. 2 shows a conventional hydrogen annealing process performed during a conventional manufacturing process of a CMOS image sensor.
FIG. 3 shows an image sensor device according to the present invention.
Please refer to FIG. 3 showing an image sensor device 200 according to the present invention. The image sensor device 200 comprises a semiconductor substrate 210, a pixel array region 202, a logic region 206, and an optical black region 204. The pixel array region 202 is on the semiconductor substrate 210 and comprises a photo sensing unit array 214. The logic region 206 is on the semiconductor substrate 210 and comprises a peripheral circuit. The optical black region 204 is positioned between the pixel array region 202 and the logic region 206 on the semiconductor substrate and comprises a photo sensing unit 215 on the semiconductor substrate 210, a first planarized layer 216 on the photo sensing unit 215, a second planarized layer 224 on the first planarized layer 216, and a optical black layer 236 on the second planarized layer 224.
It is noted that the optical black layer 236 comprises a metal layer formed at a low temperature, for example less than 400° C. The metal layer may comprise titanium, or a combination of titanium and titanium nitride.
The photo sensing unit array 214 may comprise a photodiode correspondingly electrically connecting to at least one MOS transistor. The pixel array region 202 comprises, in addition to the photo sensing unit array 214, a plurality of isolation structures 212 used to isolate each of the photo sensing units, a planarized layer (which may be the first planarized layer 216 mentioned above) covering the photo sensing unit array 214 and the isolation structures 212, a patterned metal layer 218 as a light shielding layer on the planarized layer for light shielding, another planarized layer (may be a multilayer structure, such as the second planarized layer 224 mentioned above) on the patterned metal layer 218 on the first planarized layer, a color filter array 234 on the planarized layer corresponding to the photo sensing unit array 214, and a microlens array 240 on the color filter array 234.