US 7,547,572 B2 · Method of protecting semiconductor chips from mechanical and ESD damage during handling

Abstract

A method and apparatus are provided for protecting a semiconductor device from damage. The method includes the steps of providing a active semiconductor device on a surface of the semiconductor substrate where the active device is surrounded by inactive semiconductor areas and providing a soft metallic guard ring only in the inactive semiconductor areas around the periphery of the active device wherein the metallic guard ring is connected to ground potential and not to the active device.

Drawings

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Drawings

Claims13

Dependent claims

A method of protecting a semiconductor device from damage comprising:

providing an active semiconductor device on a surface of the semiconductor substrate where the active semiconductor device is directly surrounded by inactive semiconductor areas;
and
providing a soft metallic guard ring only in the inactive semiconductor areas around the periphery of the active semiconductor device wherein the soft metallic guard ring is connected to ground potential and not to the active semiconductor device, the soft metallic guard ring being softer than the semiconductor substrate;
wherein the active semiconductor device on the surface of the semiconductor substrate further comprises a semiconductor wafer with a plurality of active semiconductor devices wherein each active semiconductor device is separated from other active semiconductor devices of the plurality of active semiconductor devices by inactive areas not containing an active semiconductor device and each active semiconductor device of the plurality of active semiconductor devices is surrounded by a soft metallic guard ring;
further comprising separating the wafer into a plurality of die wherein each die of the plurality of die contains a single active semiconductor device with the soft metallic guard ring;
further comprising removing a die from the wafer using a pick and place tool such that any mechanical damage to a die caused by the pick and place tool appears as a mark in the soft metallic guard ring and static electricity from the pick and place tool is dissipated to ground potential through the soft metallic guard ring.

3 more elements

Apparatus for protecting a semiconductor device from damage comprising:

a semiconductor body having a surface including an active semiconductor device directly surrounded by inactive semiconductor areas;
a grounding element disposed on said semiconductor body and peripherally surrounding said active semiconductor device only in the inactive semiconductor areas directly surrounding the active semiconductor device for preventing accidental ESD damage to said device by discharging any external object coming into proximate disposition to said body;
wherein the semiconductor body having the surface including the active semiconductor device further comprises a semiconductor wafer with a plurality of active semiconductor devices wherein each active semiconductor device of the plurality of active semiconductor devices is separated from other active semiconductor devices of the plurality of active semiconductor devices on the wafer by inactive areas not containing an active semiconductor device and each active semiconductor device of the plurality of active semiconductor devices is surrounded by the grounding element;
further comprising separating the wafer into a plurality of die wherein each die of the plurality of die contains an active semiconductor device with the grounding element;
further comprising removing a die from the wafer using a pick and place tool such that any mechanical damage to a die caused by the pick and place tool also appears as a mark in the grounding element and static electricity from the pick and place tool is dissipated to ground potential through the grounding element.

2 more elements

Dependencies are inferred from the claim text.

Description1,868 words

Summary588 words

#The field of the invention relates to semiconductors and more particularly to methods of semiconductor design and processing.

#Methods of manufacturing vertical cavity surface emitting laser (VCSEL) chips are generally known. However, one of the impediments to the successful manufacturing of such devices is the susceptibility of such devices to damage. In addition to physical damage, VCSELs and photodioes may be subject to electrostat discharge (ESD) or electrical over-stress (EOD) damage.

#Two market trends are driving VCSEL and photodiode chip design towards a regime where die damage during handling is more and more likely. The first trend has to do with smaller active regions. Smaller active regions (volumes) are needed for higher speeds (e.g., 4 Gb/s, 10 Gb/s applications), modal control (e.g., sensing applications, optical mice, etc.) or both. ESD/EOS damage thresholds fall as one over the square of the optical aperture size of such devices.

Brief description of the drawings6 figures

#FIG. 1 is a top plan view of a wafer under an illustrated embodiment of the invention;

#FIG. 2 is a side cut-away view of the wafer of FIG. 1;

#FIG. 3 is a top view of a chip of the wafer of FIG. 1;

Detailed description1,176 words

#FIG. 1 depicts a wafer 10 of semiconductor devices 12, 14, 16, 18 fabricated in accordance with an illustrated embodiment of the invention. FIG. 3 is an exemplary semiconductor chip 20 formed by separating the wafer 10 and where each chip 20 contains one of the semiconductor devices 12, 14, 16, 18. FIGS. 4 and 5 show alternative cut-away side views of the chip 20. The semiconductor devices 12, 14, 16, 18 may be VCSEL lasers or photodiodes and may be either arrays or single devices.

#In addition to the semiconductor device 12, 14, 16, 18, each chip 20 is provided with a guard ring 22 (FIG. 3) for mechanically protecting the optical aperture of the semiconductor device 12, 14, 16, 18 from mechanical damage as well as to provide a harmless discharge path for any charge that may build up on pickup tools. If severe mechanical damage does occur, the guard ring is designed to provide a clear visual indicator of damage thereby increasing the likelihood that the chip 20 will be discarded before being used.

#Turning now to the drawings, the wafer 10 may be divided into a grid of chip areas 13, 15, 17, 19 (where each chip area may be as depicted as shown in FIG. 3). The active areas 26 of the wafer 10 are separated from other active areas 26 (and surrounded) by inactive areas 28 (where the inactive areas 28 do not include any other active devices).

Facts

Application

11/280,378Filed 16 Nov 2005

Published

US 2007/0111378 A117 May 2007

Granted

16 Jun 2009

Term ends

27 Mar 2027

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 496 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification8 codes

H01S 5/30
Semiconductor lasers: structure or shape of the active region; Materials used for the active region
H10D 84/00
Integrated devices formed in or on semiconductor substrates that comprise only semiconducting
H10D 89/601
Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]:…
H10W 42/00
Arrangements for protection of devices

Timeline

16 Nov 2005Application filedUS 11/280,378
16 Nov 2005Assigned to Emcore Corporationassignment of assignor's interest
17 May 2007PublishedUS 2007/0111378 A1
12 Nov 2008Assigned to Bank of America, N.A.security agreement
16 Jun 2009GrantedUS 7,547,572 B2
18 May 2011Assigned to Wells Fargo Bank, National Associationsecurity agreement
12 Oct 2011Assigned to Emcore Corporation, Emcore Solar Power, Inc.release of security interest
23 Aug 2022Assigned to Emcore Corporation, Emcore Solar Power, Inc.release of security interest
12 Oct 2026TodayWithin its term
27 Mar 2027Term endsEstimated, includes 496 days of adjustment

Method of protecting semiconductor chips from mechanical and ESD damage during handling

Life of this patent

Method of protecting semiconductor chips from mechanical and ESD damage during handling

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims13

Description1,868 words

Drawings

Classification8 codes

Life of this patent

Description1,868 words