Sense amplifier with leakage testing and read debug capability
AssigneeCypress Semiconductor Corporation
InventorsVijay Kumar Srinivasa Raghavan, Ryan Tasuo Hirose
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Abstract
Disclosed is a high speed and power efficient dual mode sense amplifier circuit, which comprises a configuration selector further comprising a read amplifier, a debug circuit and a backup read circuit. The dual mode sense amplifier circuit also comprises a controllable input node further comprising an enabling circuit, the controllable input node being coupled to the configuration selector and the dual mode sense amplifier circuit comprises a differential signal generator further comprising a reference signal source, the differential signal generator is coupled to the controllable input node. A method of dual mode sensing and other embodiments are also disclosed.
Claims14
A circuit, comprising:
- a configuration selector comprising a read amplifier, a debug circuit and a backup read circuit;
- a controllable input node comprising an enabling circuit, the controllable input node coupled to the configuration selector;
- and
- a differential signal generator comprising a reference signal source, the differential signal generator is coupled to the controllable input node,
- wherein said configuration selector is operable to selectively couple a signal to disable data latching and further operable to enable linear amplification in a storage cell responsive to a delayed generation of different signals generated by said differential signal generator.
A method, comprising:
- generating differential signals responsive to a comparison between a reference signal and a data storage value;
- enabling data latching in a storage cell;
- disabling data latching and enabling linear amplification in the storage cell responsive to a delayed generation of differential signals;
- and
- enabling memory array leakage characterization.
Dependencies are inferred from the claim text.