Partial dead code elimination optimizations for program code conversion

A computer-readable storage medium having software resident thereon in the form of computer-readable code executable by a target computer system to perform the following steps to perform dynamic binary translation to convert subject program code executable on a subject computing architecture into target code executed by a target computing system, the steps comprising:

• grouping together a plurality of basic blocks of the subject program code to form a group block;
• decoding the plurality of basic blocks of the subject program code in the group block;
• generating an intermediate representation from said plurality of basic blocks of the subject program code in the group block, wherein the intermediate representation comprises nodes and links arranged as a directed acyclic graph representing expressions, calculations and operations performed by the subject program code, including one or more nodes representing a register definition by the subject program code;
• performing a partial dead code elimination optimization on said intermediate representation to generate an optimized intermediate representation, wherein the partial dead code elimination optimisation traverses the intermediate representation to create a liveness analysis indicating when the register definition represented by the one or more nodes is a partially dead register definition which is live in one path and dead in another path through the group block;
• generating target code from said optimized intermediate representation;
• and
• executing said target code on said target computing system.

A computer apparatus comprising:

• a processor;
• a memory;
• and
• translator code stored in the memory and executed by the processor to perform dynamic binary translation to convert subject program code executable on a subject processor into target code executed by the processor interleaved with execution of the translator code, said translator code comprising code executed by said processor for performing the following steps:
• grouping together a plurality of basic blocks of the subject program code to form a group block;
• decoding the plurality of basic blocks of the subject program code in the group block;
• generating an intermediate representation from said plurality of basic blocks of the subject program code in the group block, wherein the intermediate representation comprises nodes and links arranged as a directed acyclic graph representing expressions, calculations and operations performed by the subject program code, including one or more nodes representing a register definition by the subject program code;
• performing a partial dead code elimination optimization on said intermediate representation to generate an optimized intermediate representation, wherein the partial dead code elimination optimisation traverses the intermediate representation to create a liveness analysis indicating when the register definition represented by the one or more nodes is a partially dead register definition which is live in one path and dead in another path through the group block;
• generating target code from said optimized intermediate representation;
• and
• executing said target code on the processor.