US 7,542,345 B2Granted

Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same

AssigneeInnovative Silicon ISi SA

InventorsSerguei Okhonin, Eric Carman, Mark-Eric Jones

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Abstract

There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc.) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory).

Claims25

Dependent claims

An integrated circuit device comprising:

a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor includes:
a source region;
a drain region;
a body region disposed between the source region and the drain region, wherein the body region is electrically floating;
and
a gate disposed over the body region;
wherein the memory cell includes:
(i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor;
(ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor;
and
(iii) a third data state which is representative of a third charge in the body region of the electrically floating body transistor;
and
data write circuitry, coupled to the memory cell, to apply (i) first write control signals to the memory cell to write the first data state therein, (ii) second write control signals to the memory cell to write the second data state therein, and (iii) third write control signals to the memory cell to write the third data state therein;
and
wherein, in response to:
the first write control signals applied to the memory cell, the electrically floating body transistor thereof generates a first bipolar transistor current which substantially provides the first charge in the body region of the electrically floating body transistor, and
the second write control signals applied to the memory cell, the electrically floating body transistor thereof generates a second bipolar transistor current which substantially provides the second charge in the body region of the electrically floating body transistor.

14 more elements

An integrated circuit device comprising:

a memory cell array including a:
plurality of word lines;
plurality of source lines;
plurality of bit lines;
and
plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes an electrically floating body transistor, wherein the electrically floating body transistor includes:
a source region coupled to an associated source line;
a drain region coupled to an associated bit line
a body region disposed between the source region and the drain region, wherein the body region is electrically floating;
a gate disposed over the body region and coupled to an associated word line;
and
wherein each memory cell includes more than three data states, including:
(i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor;
(ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor;
(iii) a third data state which is representative of a third charge in the body region of the electrically floating body transistor;
and
(iv) a fourth data state which is representative of a fourth charge in the body region of the electrically floating body transistor;
and
data write circuitry, coupled to each of the memory cells, to apply (i) first write control signals to the memory cells to write the first data state therein, (ii) second write control signals to the memory cells to write the second data state therein, (iii) third write control signals to the memory cells to write the third data state therein and (iv) fourth write control signals to the memory cells to write the fourth data state therein;
and
wherein, in response to:
the first write control signals applied to a selected memory cell, the electrically floating body transistor thereof generates a first bipolar transistor current which substantially provides the first charge in the body region of the electrically floating body transistor,
the second write control signals applied to the selected memory cell, the electrically floating body transistor thereof generates a second bipolar transistor current which substantially provides the second charge in the body region of the electrically floating body transistor, and
the third write control signals applied to the selected memory cell, the electrically floating body transistor thereof generates a third bipolar transistor current which substantially provides the third charge in the body region of the electrically floating body transistor.

21 more elements

An integrated circuit device comprising:

a memory cell array including a:
plurality of word lines;
plurality of source lines;
plurality of bit lines;
and
plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes an electrically floating body transistor, wherein the electrically floating body transistor includes:
a source region coupled to an associated source line;
a drain region coupled to an associated bit line;
a body region disposed between the source region and the drain region, wherein the body region is electrically floating;
a gate disposed over the body region and coupled to an associated word line;
and
wherein each memory cell includes more than two data states, including:
(i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor;
(iii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor;
and
(iii) a third data state which is representative of a third charge in the body region of the electrically floating body transistor;
and
data sense circuitry, coupled to the plurality of memory cells, to sense the data state of the plurality of memory cells;
and
wherein, in response to read control signals applied to a selected memory cells, the electrically floating body transistor of the selected memory cell generates a read bipolar transistor current which is representative of the data state of the selected memory cell and wherein the data sense circuitry determines the data state of the selected memory cell at least substantially based on the read bipolar transistor current.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/703,429Filed 7 Feb 2007 · us provisional application
Priority: 16 Feb 2006
Published: US 2007/0187775 A116 Aug 2007
Granted: 2 Jun 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 30/711
Insulated-gate field-effect transistors [IGFET]: having floating bodies
G11C 7/1006
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data managing, e.g. manipulating data before…
G11C 7/16
Arrangements for writing information into, or reading information out from, a digital store: storage of analogue signals in digital stores using…
G11C 11/404
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with one charge-transfer gate, e.g. MOS transistor, per cell