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US 7,539,203 B2Granted
Multiple channel flow control with first-in-first-out (FIFO) read/write random access memory (RAM)
AssigneeIntel Corporation
InventorRajesh B. R. Rao
Life of this patent
Estimating the term…
Abstract
According to embodiments of the present invention, a data source provides data on multiple channels to a data sink. In embodiments, each channel shares the same random access memory (RAM)-based flow control and has first-in-first-out (FIFO) read/write.
Claims12
A method, comprising:
- receiving from a data source a first data on a first channel and a second data on a second channel;
- receiving a first channel identifier and a second channel identifier, the first channel identifier to identify the first channel and the second channel identifier to identify the second channel;
- determining a first memory write address for a first row in a memory using the first channel identifier;
- determining a second memory write address for a second row in the memory using the second channel identifier;
- reading at least a first counter in the first row to determine a bank in the first row into which to write the first data;
- reading at least a second counter in the second row to determine a bank in the second row into which to write the second data;
- writing in a first-in (FI) manner the first data to the first row in the memory and the second data to the second row in the memory, the first channel identifier to identify the first row and the second channel identifier to indicate the second row, wherein each channel is associated with its own row in the memory;
- reading in a first-out (FO) manner the first data from the first row and the second data from the second row;
- and
- making the first data and the second data available for access to at least one data sink.
7 more elements
An apparatus, comprising:
- logic to receive a first data on a first channel, a second data on a second channel, a first channel identifier to identify the first channel, a second channel identifier to identify the second channel;
- a memory having at least a first row and a second row, each row to be written in a first-in (FI) manner and to be read in a first-out (FO) manner, the first data to be written to and read from the first row and the second data to be written to and read from the second row, the first channel identifier to identify the first row and the second channel identifier to indicate the second row, wherein each channel is associated with its own row in the memory;
- a first indicator to indicate a byte order for the first data or a second indicator to indicate a byte order for the second data;
- and
- second logic to order the first data according to the first indicator or the second data according to the second indicator.
2 more elements
Dependencies are inferred from the claim text.