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US 7,538,590 B2Granted
Methods and apparatus for dividing a clock signal
AssigneeMicron Technology, Inc.
InventorFeng Lin
Life of this patent
Estimating the term…
Abstract
There is provided a true single phase logic clock divider that is configured to divide a clock signal by increments of two, three, four, or six. Because the true single phase logic clock divider is based on true single phase logic instead of static logic, the true single phase logic clock divider is able to reliably divide clock signals that could not reliably be divided by clock dividers based on static logic gates. There is also provided a method comprising receiving an input signal with a frequency between 2.5 gigahertz and 4 gigahertz and producing an output signal with a frequency approximately one-third of the frequency of the input signal.
Claims12
A clock divider comprising:
- a first clock divider circuit comprising:
- a first transistor coupled to a first input of the first clock divider circuit and configured to receive a first input signal;
- a second transistor coupled in parallel to the first transistor and configured to receive a second input signal;
- a third transistor coupled to the first input and configured to receive the first input signal and coupled in series with both the first transistor and the second transistor;
- a fourth transistor coupled directly to ground, coupled in series with the third transistor and coupled to a second input of the first clock divider circuit, the fourth transistor configured to receive the second input signal;
- a fifth transistor coupled to the first and second transistors and configured to receive a clock signal, wherein the clock signal is independent of the first input signal, the second input signal, or an inversion of the first input signal or the second input signal;
- and
- a second clock divider circuit coupled to the first clock divider circuit and configured substantially similarly to the first clock divider circuit, wherein an output of the second clock divider circuit is coupled to the first input of the first clock divider circuit.
5 more elements
A clock divider comprising:
- a first clock divider circuit comprising:
- a first transistor coupled to a first input of the first clock divider circuit and configured to receive a first input signal;
- a second transistor coupled in parallel to the first transistor and configured to receive a second input signal;
- a third transistor coupled to the first input and configured to receive the first input signal and coupled in series with both the first transistor and the second transistor;
- a fourth transistor coupled directly to ground, coupled in series with the third transistor and coupled to a second input of the first clock divider circuit, the fourth transistor configured to receive the second input signal;
- a fifth transistor coupled to the first and second transistors and configured to receive a clock signal, wherein the clock signal is independent of the first input signal, the second input signal, or an inversion of the first input signal or the second input signal;
- and
- a second clock divider circuit coupled to the first clock divider circuit and configured substantially similarly to the first clock divider circuit, wherein an output of the first clock divider circuit is coupled to an inverter and wherein the inverter is coupled to a first input of the second clock divider.
5 more elements
A method of manufacturing a clock divider comprising:
- coupling a first transistor to a first input of a first clock divider circuit and configuring the first transistor to receive a first input signal;
- coupling a second transistor in parallel to the first transistor and configuring the second transistor to receive a second input signal;
- coupling a third transistor to the first input and in series with both the first transistor and the second transistor and configuring the third transistor to receive the first input signal;
- coupling a fourth transistor directly to ground, in series with the third transistor and to a second input of the first clock divider circuit, and configuring the fourth transistor to receive the second input signal;
- coupling a fifth transistor to the first and second transistors, and configuring the fifth transistor to receive a clock signal, wherein the clock signal is independent of the first input signal, the second input signal, or an inversion of the first input signal or the second input signal;
- coupling a second clock divider circuit to the first clock divider circuit and configuring the second clock divider circuit substantially similarly to the first clock divider circuit, and coupling an output of the second clock divider circuit to the first input of the first clock divider circuit.
3 more elements
Dependencies are inferred from the claim text.