Calibration technique for measuring gate resistance of power MOS gate device at water level
AssigneeAlpha and Omega Semiconductor Incorporated
InventorsAnup Bhalla, Sik K. Lui, Daniel Ng
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Abstract
This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the RC network to prepare for carrying out a wafer-level measurement calibration of the semiconductor power device. The method further includes a step of connecting a probe card to a set of contact pads on the semiconductor wafer for carrying out the wafer-level measurement calibration followed by performing a gate resistance Rg measurement for the semiconductor power chips.
Claims9
A semiconductor wafer comprising:
- a plurality of MOSFET chips disposed thereon wherein said semiconductor wafer further comprises a test structure built with a resistor-capacitor (RC) network;
- and
- a resistance value of said RC network in a range approximately the same that of a gate resistance of said MOSFET chips and a capacitance value of said RC network in a range approximately the same that of a gate capacitance of said MOSFET chips.
A semiconductor wafer comprising:
- a plurality of semiconductor power chips disposed on a semiconductor wafer wherein said semiconductor wafer further comprises a test area built with a resistor-capacitor (RC) network with a resistance and capacitance and ready for carrying a wafer-level semiconductor power device measurement calibration;
- and
- a resistance value of said RC network in a range approximately the same that of a gate resistance of said MOSFET chips and a capacitance value of said RC network in a range approximately the same that of a gate capacitance of said MOSFET chips.
A semiconductor device comprising:
- a plurality of semiconductor chips disposed on a semiconductor wafer wherein said semiconductor wafer further comprises a test area built with a resistor-capacitor (RC) network with ready for carrying a wafer-level semiconductor device measurement calibration;
- and
- a resistance value of said RC network in a range approximately the same that of a gate resistance of said MOSFET chips and a capacitance value of said RC network in a range approximately the same that of a gate capacitance of said MOSFET chips.
Dependencies are inferred from the claim text.