High voltage non punch through IGBT for switch mode power supplies
AssigneeInternational Rectifier Corporation
InventorsRichard Francis, Chiu Ng
Life of this patent
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Abstract
A process for forming an NPT IGBT in a thin N type silicon wafer in which the bottom surface of a thin silicon wafer (100 microns thick or less) has a shallow reduced lifetime region in its bottom formed by a light species atom implant to a depth of less than about 2.5 microns. A P+ transparent collector region about 0.5 microns deep is formed in the bottom of the damaged region by a boron implant. A collector contact of Al/Ti/NiV and Ag is sputtered onto the collector region and is annealed at 200° C. to 400° C. for 30 to 60 minutes. A pre-anneal step before applying the collector metal can be carried out in vacuum at 300° C. to 400° C. for 30 to 60 seconds.
Claims12
A process for the preparation of the backside of an IGBT die;
- said IGBT comprising a silicon wafer of one of the conductivity types having a top side which contains junctions to define an IGBT and a bottom side which receives an emitter contact, said process comprising the implant of a light species atom into said bottom side to damage the silicon lattice of said wafer to a given depth to define a reduced lifetime region in said wafer for said given depth;
- and thereafter forming a shallow transparent collector region of the other conductivity type in the bottom of said reduced lifetime region;
- and thereafter forming a conductive metal contact on said collector region, and thereafter annealing at a temperature below 400° C. to remove damage caused by said implant of said light species.
Dependencies are inferred from the claim text.