Prefetch hardware efficiency via prefetch hint instructions

A system including:

• a storage array;
• an access pattern recognizer coupled to the storage array;
• wherein the storage array is enabled to record a plurality of pattern identifiers, each of the pattern identifiers specifying a respective series of addresses to search for in a stream of addresses, wherein the stream of addresses are generated during execution of an object program, and wherein the object program explicitly specifies the pattern identifiers embedded therein;
• and
• wherein the pattern identifiers are compatible with identifying at least one of:
• no pattern,
• a sparse pattern,
• a one-dimensional stride pattern,
• a two-dimensional stride pattern,
• a multi-dimensional stride pattern,
• a indirect-stride pattern, and
• an indirect pattern.

A system including:

• a processor;
• a table having a plurality of entries;
• a memory reference analyzer coupled to the table and responsive to a first stream of memory addresses from a first memory access generator;
• a second memory access generator enabled to generate a second stream of memory addresses, the second memory access generator being coupled to the memory reference analyzer and responsive to a memory hierarchy promotion request;
• wherein the memory reference analyzer produces the memory hierarchy promotion request subject to a memory access pattern as specified by one of the entries of the table being detected in the first stream of memory addresses;
• and
• wherein the one entry is produced in response to a memory hierarchy promotion directive embedded in an executable program, wherein the memory hierarchy promotion directive explicitly defines the memory access pattern.

A computer readable storage medium having a set of instructions stored therein which when executed by a processing element causes the processing element to perform steps including:

• selecting one of a plurality of a prefetch hints based on recognition of a memory reference idiom specified by a source program;
• embedding the selected one of the prefetch hints into an executable representation of the source program, wherein the selected one of the prefetch hints explicitly defines a memory access pattern, the executable representation being compatible with execution on a processor, the execution producing at least memory traffic;
• and
• wherein the processor includes a hint pattern recognizer enabled to recognize a portion of the memory traffic matching the memory access pattern.