Data structures and circuit for multi-channel data transfers using a serial peripheral interface

Abstract

A serial interface controller provides for transferring data between a data source having a least one channel and a processor. The serial interface controller has a plurality of control registers; the control registers in turn include a data structure for configuring the serial interface controller for a data transfer. That data structure further comprises a field for selectively setting the serial interface controller in its run mode or its configuration mode; a field for storing the I/O mode of the serial interface controller; a field for storing the address of the active data channel; and, a field for storing the system clock rate. In the preferred embodiment, the control registers include fields for device identification, a flag for the run or configure mode, a I/O-mode control, a value for the channels active (in multi-channel implementations), the data source clock rate, the ADC clock rate, channel-status flags, the CIC decimation rate, the number of taps for FIR filters, and the filter coefficients corresponding to the number of FIR taps in a particular data source.

Dependencies are inferred from the claim text.