Methods and apparatus for clock and data recovery using a single source
AssigneeNet Logic Microsystems, Inc.
InventorsStefanos Sidiropoulos, Marc J. Loinaz
Life of this patent
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AssigneeNet Logic Microsystems, Inc.
InventorsStefanos Sidiropoulos, Marc J. Loinaz
Estimating the term…
A receiver circuit reduces the need for external clock sources such as crystal oscillators. The receiver circuit makes use of only a single source, the data input, for performing clock and data recovery. A clock and data recovery circuit receives data and at least one reference clock. The clock and data recovery circuit recovers the clock for the input data using the data input and a reference clock. A clean-up phase lock loop circuit reduces jitter in the recovered clock. The recovered clock from the clock and data recovery circuit is input to the clean-up phase lock loop to produce a clean clock. The clean clock is feed into a clock reference circuit. The clock reference circuit generates the reference clock for the clock and data recovery circuit. As such, the reference clock is based on feed back from the recovered clock. The clock and data recovery circuit obtains a meta-stable state because the loop bandwidth of the clean-up phase lock loop is substantially less than a loop bandwidth for the phase lock loop in the clock reference generator circuit. A clock and data recovery circuit, which does not use a clean-up phase lock loop, is also disclosed. For this configuration, the recovered clock, output from the clock and data recovery circuit, is input directly to the clock reference circuit.
A circuit comprising:
A circuit comprising:
A method for clock and data recovery, said method comprising:
Dependencies are inferred from the claim text.