US 7,531,836 B2 · Body bias compensation for aged transistors

Abstract

Embodiments of the invention include on-chip transistor degradation detection and compensation. In one embodiment of the invention, an integrated circuit is provided including a circuit with a body bias terminal coupled to a body of one or more transistors to receive a body bias voltage; a programmable degradation monitor to detect aging of transistors, and a body bias voltage generator coupled to the circuit and the programmable degradation monitor. The body bias voltage generator to adjust the body bias voltage coupled into the circuit in response to transistor aging detected by the programmable degradation monitor. The programmable degradation monitor includes a reference ring oscillator, an aged ring oscillator, and a comparison circuit. The comparison circuit to compare data delays in the reference ring oscillator and the aged ring oscillator to detect transistor aging within the integrated circuit.

Claims23

Dependent claims

An integrated circuit comprising:

a circuit including a body bias terminal coupled to a body of one or more transistors to receive a body bias voltage;
a programmable degradation monitor to detect aging of transistors, the programmable degradation monitor including a reference ring oscillator, an aged ring oscillator, and a comparison circuit, the comparison circuit to compare data delay in the reference ring oscillator and the aged ring oscillator to detect transistor aging within the integrated circuit;
and
a body bias voltage generator coupled to the circuit and the programmable degradation monitor, the body bias voltage generator to adjust the body bias voltage coupled into the circuit in response to transistor aging detected by the programmable degradation monitor.

1 more element

A programmable degradation monitor comprising:

a reference ring oscillator to provide a reference frequency signal and a reference delay signal in response to a data input signal;
a degradable ring oscillator to provide an aged frequency signal and an aged delay signal in response to the data input signal;
and a comparison circuit coupled to the reference ring oscillator and the degradable ring oscillator, the comparison circuit to compare the reference delay signal with the aged delay signal to detect transistor aging within an integrated circuit.

A system comprising:

an integrated circuit including
a fast circuit including one or more transistors with a body bias terminal to receive a body bias voltage and a source terminal to receive a power supply voltage, and
a programmable degradation monitor to detect degradation of transistors, the programmable degradation monitor including a reference ring oscillator, a degradable ring oscillator, and a comparison circuit, the comparison circuit to compare data delay in the reference ring oscillator and the degradable ring oscillator to detect transistor degradation within the integrated circuit;
and
a body bias voltage generator coupled to the fast circuit and the programmable degradation monitor of the integrated circuit, the body bias voltage generator to adjust either the body bias voltage or the power supply voltage coupled into the transistors of the fast circuit in response to transistor degradation detected by the programmable degradation monitor.

2 more elements

Dependencies are inferred from the claim text.

Body bias compensation for aged transistors

Life of this patent

Body bias compensation for aged transistors

Life of this patent

Abstract

Claims23