Memory device internal parameter reliability
AssigneeMicron Technology, Inc.
InventorsVipul Patel, Theodore T. Pekny
Life of this patent
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Abstract
Embodiments herein may store redundant copies of an operational parameter associated with an internal operation of a memory device. The redundant copies and associated parity bits may be stored in sets of writeable, non-volatile storage cells. A working area of the memory device may subsequently be populated with one or more redundant copies of the operational parameter, with a flag associated with the operational parameter, or with both. Other embodiments may be described and claimed.
Claims32
An apparatus, including:
- first and second sets of writeable, non-volatile storage cells in a memory device to contain first and second redundant copies of an operational parameter associated with the memory device;
- at least one first parity bit associated with the first redundant copy of the operational parameter;
- at least one second parity bit associated with the second redundant copy of the operational parameter;
- and
- an error control module coupled to the first and second sets of storage cells to increase a likelihood of an error-free retrieval of the operational parameter by attempting a parity error-free read from at least one of the first set of storage cells or the second set of storage cells.
A system, including:
- a portable electronic device (PED);
- a memory module associated with the PED;
- and
- first and second sets of writeable, parity-protected, non-volatile storage cells associated with the memory module to contain first and second redundant copies of an operational parameter associated with the memory module.
A method, including:
- storing a plurality of redundant copies of an operational parameter associated with an internal operation of a memory device and at least one parity bit associated with each one of the plurality of redundant copies in a plurality of sets of writeable, non-volatile storage cells;
- populating a working area of the memory device with at least one of a first redundant copy of the operational parameter or a flag associated with the first redundant copy if the first redundant copy is read without a parity error;
- and
- populating the working area of the memory device with at least one of a second redundant copy of the operational parameter or a flag associated with the second redundant copy if a first condition is satisfied.
A computer-readable medium having instructions, wherein the instructions, when executed, result in at least one processor performing:
- storing a plurality of redundant copies of an operational parameter associated with an internal operation of a memory device and at least one parity bit associated with each one of the plurality of redundant copies in a plurality of sets of writeable, non-volatile storage cells;
- populating a working area of the memory device using a first redundant copy of the operational parameter if the first redundant copy is read without a parity error;
- and
- populating the working area of the memory device using a second redundant copy of the operational parameter if a first condition is satisfied.
Dependencies are inferred from the claim text.