Clock enable throttling for power savings in a memory subsystem
AssigneeSun Microsystems, Inc.
InventorsSanjiv Kapil, Aaron S. Wynn
Life of this patent
Estimating the term…
Abstract
A memory subsystem is disclosed. The memory subsystem includes a memory controller coupled to one or more memory modules. Each memory module comprises a buffer coupled to one or more memory ranks. A clock source is coupled to provide a clock signal to each of the memory modules. The memory controller is configured to convey a clock enable (CKE) command to one of the memory modules, the CKE command corresponding to a given memory rank. In response to the CKE command, a memory module buffer associated with the given memory rank is configured to convey a CKE disable signal to the given memory rank. The given memory rank is configured to disable operation of the clock signal within the given memory rank, responsive to the CKE disable signal.
Claims23
A memory subsystem comprising:
- a memory controller coupled to one or more memory modules, each memory module comprising a buffer coupled to a plurality of memory ranks;
- and
- a clock source coupled to provide a clock signal to each of the memory modules;
- wherein the memory controller is configured to convey a clock enable (CKE) command to at least one of the memory modules, the CKE command including a plurality of CKE signals, each corresponding to a respective one of the plurality of memory ranks of the at least one of the memory modules;
- wherein in response to the CKE command:
- a memory module buffer is configured to convey a CKE disable signal to each memory rank for which the corresponding one of the plurality of CKE signals has a first value;
- and
- each memory rank is configured to disable operation of the clock signal within at least a portion of the memory rank, responsive to the CKE disable signal.
A method in a memory subsystem, the method comprising:
- providing a clock signal to one or more memory modules, each memory module comprising a buffer coupled to a plurality of memory ranks;
- receiving in a first memory module of the memory modules a clock enable (CKE) command, the CKE command including a plurality of CKE signals, each corresponding to a respective one of the plurality of memory ranks of the at least one of the memory modules;
- conveying from a buffer in the first memory module a CKE disable signal to each memory rank for which the corresponding one of the plurality of CKE signals has a first value, responsive to the CKE command;
- and
- disabling operation of the clock signal within at least a portion of each memory rank that receives a CKE disable signal.
A processor comprising:
- a memory controller configured to be coupled to one or more memory modules, each memory module comprising a buffer coupled to a plurality of memory ranks;
- wherein the processor is configured to generate and convey memory access requests to the memory controller;
- and
- wherein the memory controller configured to:
- convey a clock enable (CKE) command to at least one of the memory modules, the CKE command including a plurality of CKE signals, each corresponding to a respective one of the plurality of memory ranks of the at least one of the memory modules;
- wherein in response to the CKE command:
- a memory module buffer is configured to convey a CKE disable signal to each memory rank for which the corresponding one of the plurality of CKE signals has a first value;
- and
- each memory rank is configured to disable operation of the clock signal within at least a portion of the memory rank, responsive to the CKE disable signal.
A memory module comprising:
- a plurality of memory ranks;
- and
- a buffer configured to interconnect a memory controller and the a plurality of memory ranks;
- wherein in response to receiving a CKE command from the memory controller including a plurality of CKE signals, each corresponding to a respective one of the plurality of memory ranks, the buffer is configured to convey a CKE disable signal to each memory rank for which the corresponding one of the plurality of CKE signals has a first value;
- and
- wherein each memory rank is configured to disable operation of the clock signal within at least a portion of the memory rank, responsive to the CKE disable signal.
Dependencies are inferred from the claim text.