Coherence of displayed images for split-frame rendering in multi-processor graphics system
AssigneeNVIDIA Corporation
InventorsFranck R. Diard, Philip Browning Johnson, Wayne Douglas Young, Herbert O. Ledebohm
Life of this patent
Estimating the term…
Abstract
Coherence of displayed images is provided for a graphics processing systems having multiple processors operating to render different portions of a current image in parallel. As each processor completes rendering of its portion of the current image, it generates a local ready event, then pauses its rendering operations. A synchronizing agent detects the local ready event and generates a global ready event after all of the graphics processors have generated local ready events. The global ready signal is transmitted to each graphics processor, which responds by resuming its rendering activity.
Claims16
A method for rendering images in a graphics processor in synchronization with one or more other graphics processors, the method comprising:
- executing a first group of rendering commands, wherein execution of the first group of rendering commands includes writing pixel data for a portion of a current image to a first frame buffer;
- concurrently with the act of executing the first group of rendering commands, scanning out pixel data for a portion of a previous image from a second frame buffer;
- after executing the first group of rendering commands, transmitting a flip interrupt signal to a central processing unit;
- subsequently to generating the flip interrupt signal, detecting a global ready signal received from the central processing unit, wherein the global ready signal indicates that each of the one or more other graphics processors has also generated a respective flip interrupt signal;
- and
- in response to detecting the global ready signal, executing a second group of rendering commands, wherein execution of the second group of rendering commands includes writing pixel data for a next image to the second frame buffer.
A method for synchronizing buffer transitions among a plurality of graphics processors, wherein the graphics processors are operable in parallel to write pixel data for a portion of a current image to respective first frame buffers while scanning out a portion of a previous image from respective second frame buffers, the method comprising, by a central processing unit:
- transmitting a stream of rendering commands to the plurality of graphics processors, the stream of rendering commands including one or more commands directing each of the graphics processor to write pixel data for the portion of the current image associated with the respective one of the graphics processors to the respective first frame buffer;
- receiving from each of the graphics processors a respective flip interrupt signal, each flip interrupt signal indicating completion of writing of the pixel data for the portion of the current image associated with the respective one of the graphics processors;
- after receiving the respective flip interrupt signals from all of the graphics processors, transmitting a global ready signal to each of the graphics processors,
- wherein, in response to the global ready signal, each of the graphics processors begins to write pixel data for a respective portion of a next image to the respective second frame buffer.
A graphics processing system comprising:
- a central processing unit having an interrupt servicing module;
- and
- a plurality of graphics processors communicably coupled to the central processing unit and configured to render different portions of an image in parallel, each of the graphics processors having:
- a first frame buffer and a second frame buffer;
- a rendering module configured to execute a stream of commands received from the central processing unit, the stream of commands including:
- a first group of rendering commands instructing the graphics processor to write pixel data for a portion of a current image to the first frame buffer;
- a second group of rendering commands instructing the graphics processor to write pixel data for a portion of a next image to the second frame buffer;
- an interrupt command instructing the graphics processor to transmit a flip interrupt to the central processing unit, wherein the interrupt command occurs in the stream after the first group of rendering commands and before the second group of rendering commands;
- and
- a hold command instructing the graphics processor to pause execution of further commands until a global ready signal is received from the central processing unit, wherein the hold command occurs in the stream after the interrupt command and before the second group of rendering commands, wherein the interrupt servicing module is configured to detect flip interrupts from each of the graphics processors and to generate the global ready signal after all of the graphics processors have generated their respective flip interrupts.
Dependencies are inferred from the claim text.