System and method for performing decimal division

A system for performing decimal division, the system comprising:

• input registers for storing a scaled divisor and a scaled dividend;
• a plurality of multiples registers for storing a subset of the multiples of the scaled divisor;
• and
• a mechanism including a two cycle adder, a latching multiplexer connected to the multiples registers and the two cycle adder, a remainder register connected to the two cycle adder, remainder selection circuitry connected to the remainder register, quotient selection circuitry connected to the multiplexer, the remainder selection circuitry and the remainder register, and a quotient accumulator connected to the two cycle adder, the mechanism:
• receiving the scaled divisor and dividend into the input registers;
• storing a subset of the multiples of the scaled divisor in the multiples registers;
• initializing an accumulated quotient to zero;
• initializing a first current remainder to be equal to the scaled dividend;
• initializing a second current remainder to be equal to the scaled dividend minus the scaled divisor;
• and
• performing until a selected number of quotient digits are produced:
• calculating an estimated next quotient digit based on the first digit of the first current remainder;
• selecting a temporary remainder to be either the first current remainder or the second current remainder based on the estimated next quotient digit;
• calculating a first next remainder by subtracting one of the stored multiples from the temporary remainder using the two cycle adder, wherein the stored multiple is selected based on a first digit of the first current remainder;
• calculating a second next remainder by subtracting an other one of the stored multiples from the temporary remainder using the two cycle adder, wherein the other one of the stored multiples is selected based on the first current remainder;
• calculating an actual next quotient digit based on the estimated next quotient digit, the first current remainder and the first next remainder;
• updating the accumulated quotient with the actual next quotient digit;
• and
• setting the first current remainder to be equal to the first next remainder and the second current remainder to be equal to the second next remainder.

A system for performing decimal division, the system comprising:

• input registers for storing a scaled divisor and a scaled dividend;
• a plurality of multiples registers for storing a subset of multiples of the scaled divisor;
• and
• a pipeline mechanism including a two cycle adder, a latching multiplexer connected to the multiples registers and the two cycle adder, a remainder register connected to the two cycle adder, remainder selection circuitry connected to the remainder register, quotient selection circuitry connected to the multiplexer, the remainder selection circuitry and the remainder register, and a quotient accumulator connected to the two cycle adder, the pipeline mechanism:
• calculating quotient digits in response to the scaled divisor and the scaled dividend, the calculating including:
• selecting a new quotient digit;
• and
• calculating a new remainder using the two cycle adder, wherein input to the two cycle adder includes data from one or more of the multiples registers.