US 7,519,647 B2 · System and method for providing a decimal multiply algorithm using a double adder

Abstract

A system for performing decimal multiplication including input registers for inputting a multiplier and a multiplicand. The multiplier includes one or more digits. The system also includes one or more two cycle adders and mechanism. The mechanism receives the multiplier and the multiplicand into the input registers. A running sum is reset to zero. The mechanism also performs for each of the digits in the multiplier in order from least significant digit to most significant digit: creating a partial product of the digit and the multiplicand; and adding the partial product to the running sum using the two cycle adders. When the loop is completed for each of the digits in the multiplier, the mechanism outputs the running sum as the result.

Claims10

Dependent claims

A system for performing decimal multiplication, the system comprising:

operand registers storing a multiplier and a multiplicand, wherein the multiplier includes one or more digits;
a shifter storing a running sum, the running sum initialized to zero;
and
a mechanism including one or more two cycle adders connected to the operand registers, multiplicand multiples circuitry connected to the operand registers, and a result digits register connected to the two cycle adders, the mechanism:
performing for each of the digits in the multiplier in order from least significant digit to most significant digit:
creating a partial product of the digit and the multiplicand;
and
adding the partial product to the running sum;
and
outputting the running sum as the result of multiplying the multiplier and the multiplicand.

7 more elements

A system for performing decimal multiplication, the system comprising:

operand registers storing a multiplier and a multiplicand, wherein the multiplier includes one or more sets of two digits, the most significant set may include one digit with a leading zero digit added to create the set of two digits, each set includes a first digit and a second digit, and the second digit is less significant than the first digit;
a shifler storing a running sum, the running sum initialized to zero;
and
a mechanism including one or more two cycle adders connected to the operand registers, multiplicand multiples circuitry connected to the operand registers, and a results digits register connected to the two cycle adders, the mechanism:
performing for each set of the digits in the multiplier in order from the set containing the least significant digit to the set containing the most significant digit:
creating a first digit partial product of the first digit in the set and the multiplicand;
creating a second digit partial product of the second digit in the set and the multiplicand;
adding the first digit partial product times ten to the second digit partial product using the two cycle adders and storing the result in a total partial product;
and
adding the total partial product to the running sum using the two cycle adders;
and
outputting the running sum as the result of multiplying the multiplier and the multiplicand.

9 more elements

Dependencies are inferred from the claim text.

System and method for providing a decimal multiply algorithm using a double adder

Life of this patent

System and method for providing a decimal multiply algorithm using a double adder

Life of this patent

Abstract

Claims10