Semiconductor device
AssigneeInnovative Silicon ISi SA
InventorsPierre Fazan, Serguei Okhonin
Life of this patent
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Abstract
A semiconductor device such as a DRAM memory device is disclosed. A substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semiconductor layer (16) has source (18) and drain (20) regions formed therein to define bodies (22) of respective field effect transistors. The box region (38) is more heavily doped than the adjacent body (22), but less highly doped than the corresponding source (18) and drain (20), and modifies the valence and/or conduction band of the body (22) to increase the amount of electrical charge which can be stored in the body (22).
Claims26
An integrated circuit device, disposed on or in a first semiconductor region or layer which resides on or above an insulating region or layer, wherein the insulating region or layer is disposed on or over a substrate, the integrated circuit device comprising:
- a first portion including a plurality of transistors, wherein each transistor includes:
- a source region disposed on or in the first semiconductor region;
- a drain region disposed on or in the first semiconductor region;
- a body region disposed on or in the first semiconductor region and between the source region, the drain region, and the insulating region or layer, wherein the body region is electrically floating;
- a gate disposed over the body region;
- and
- a second portion including a plurality of transistors, wherein each transistor includes:
- a source region disposed in or on the first semiconductor region;
- a drain region disposed in or on the first semiconductor region;
- a body region disposed in or on the first semiconductor region and between the source region, the drain region, and the insulating region or layer;
- a gate disposed over the body region;
- and
- wherein the integrated circuit device further includes a second semiconductor region or layer disposed on or in the substrate and juxtaposed the body region of each transistor of the first portion of the integrated circuit device and separated therefrom by the insulating region or layer, and wherein the second semiconductor region or layer is not disposed on or in a portion of the substrate juxtaposed the body region of each transistor of the second portion of the integrated circuit device.
An integrated circuit device, disposed on or in a first semiconductor region or layer which resides on or above an insulating region or layer, wherein the insulating region or layer is disposed on or over a substrate, the integrated circuit device comprising:
- a memory portion having a plurality of partially-depleted transistors, each partially-depleted transistor includes:
- a source region disposed on or in the first semiconductor region;
- a drain region disposed on or in the first semiconductor region;
- a body region disposed on or in the first semiconductor region and between the source region, the drain region, and the insulating region or layer, wherein the body region is electrically floating;
- and
- a gate disposed over the body region;
- and
- a second portion having a plurality of fully-depleted transistors, each fully-depleted transistor includes:
- a source region disposed in or on the first semiconductor region;
- a drain region disposed in or on the first semiconductor region;
- a body region disposed in or on the first semiconductor region and between the source region, the drain region, and the insulating region or layer;
- a gate disposed over the body region.
Dependencies are inferred from the claim text.