# US 7,512,572 B2 · Digital memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,512,572 B2 - Document ID: US7512572B2 - Status: Granted - Kind: B2 - Application number: 10/509,086 - Filed: 2002-10-14 - Published: 2005-12-22 - Granted: 2009-03-31 - Earliest claimed: 2002-03-28 - Assignees: Cogniscience Limited - Inventors: Stephen B. Furber - Web page: https://patentgrep.com/patent/US7512572B2 ## CPC - G11C 8/06: Address interface arrangements, e.g. address buffers - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory configuration for use in a computer system includes a plurality of address decoders each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states. A data memory having a plurality of word lines of predetermined length, is also included in each of the address decoders and is activatable to select one of the plurality of word lines. The address decoders receive an input address having a predetermined number of bits and compare the identifier of an address decoder with the input address wherein the memory further activates an address decoder if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier. ## Claims ### Claim 1 A memory configuration for use in a computer system, the memory comprising: a plurality of address decoders, each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states; and a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select one of the plurality of word lines; the address decoders including means to receive an input address having a predetermined number of bits and means to compare the identifier of an address decoder with the input address; and wherein the memory further includes means to activate an address decoder if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier; and wherein each address decoder identifier has an equal number of bits set to the first selectable state and the means to receive an input address is configured to receive addresses containing a predetermined number of bits set to the first selectable state. ### Claim 2 (depends on 1) A memory configuration according to claim 1, wherein: the means to compare the identifier of an address decoder with the input address considers positional correspondence between bits set to the first selectable state in the input address and bits set to the first selectable state in the decoder identifiers. ### Claim 3 (depends on 1) A memory configuration according to claim 1, wherein the predetermined number of bits set to the first selectable state in an input address is equal to the number of bits set to the first selectable state in each of the address decoder identifiers. ### Claim 4 (depends on 1) A memory configuration according to claim 1, wherein the data memory comprises a plurality of single bit memories, such that each bit of each word line is stored in a single bit memory. ### Claim 5 (depends on 1) A memory configuration according to claim 1, wherein the data memory comprises a data input line containing an equal number of bits to each of the plurality of word lines. ### Claim 6 (depends on 5) A memory configuration according to claim 5, further comprising data writing means to copy data from the data input line to word lines activated by the address decoders. ### Claim 7 (depends on 5) A memory configuration according to claim 5, wherein the data input line is configured to receive input data containing a predetermined number of bits set to the first selectable state. ### Claim 8 (depends on 1) A memory configuration according to claim 1, further comprising: means to sum values stored at each bit of word lines activated by an address decoder to generate an activation level value for each bit. ### Claim 9 (depends on 7) A memory configuration according to claim 7, further comprising: means to generate an output word containing the predetermined number of bits set to the first selectable state. ### Claim 10 (depends on 9) A memory configuration according to claim 9, wherein the bits set to first selectable state in the output are the predetermined number of bits having the highest activation level. ### Claim 11 (depends on 1) A memory configuration according to claim 1, wherein the memory is implemented using a plurality of artificial neurons connected together to form a neural network. ### Claim 12 (depends on 11) A memory configuration according to claim 11, wherein the plurality of address decoders are represented by a plurality of address decoder neurons, and the data memory is represented by a plurality of data neurons. ### Claim 13 A neural network memory configuration for use in a computer system, the memory comprising: a plurality of address decoder neurons each of which is connected to a predetermined number of input neurons; a data memory having a plurality data neurons, each of the said address decoder neurons being activatable to select some of the plurality of data neurons; the address decoder neurons including means to receive a signal representing a firing of an input neuron to which it is connected; and wherein an address decoder neuron comprises means to activate data neurons if firing signals are received from at least a predetermined minimum number of input neurons to which the address decoder neuron is connected. ### Claim 14 A method for operating a memory for use in a computer system, the memory comprising: a plurality of address decoders each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states; a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select one of the plurality of word lines; wherein an input address having a predetermined number of bits is input to the address decoder, the identifier of an address decoder is compared with the input address and address decoders are activated if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier; wherein each address decoder identifier has an equal number of bits set to the first selectable state; and wherein an input address has a predetermined number of bits set to the first selectable state. ### Claim 15 (depends on 14) A method according to claim 14, wherein input data is presented at a data input of the data memory and the data is written to word lines activated by the activated address decoders. ### Claim 16 (depends on 14) A method according to claim 14, wherein the predetermined minimum number of bits is set such that fewer than 100 address decoders are activated by any valid input address. ### Claim 17 (depends on 16) A method according to claim 16, wherein the predetermined minimum number of bits is set such that fewer than 50 address decoders are activated by any valid input address. ### Claim 18 (depends on 17) A method according to claim 17, wherein the predetermined minimum number of bits is set such that fewer than 20 and more than 11 address decoders are activated by any valid input address. ### Claim 19 A method for optimizing the operation of a computer memory which comprises a plurality of address decoders each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states, a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select one of the plurality of word lines, means to receive an input address, and means to activate one or more of the address decoders if a comparison between a decoder identifier and the input address exceeds a predetermined comparison threshold; said method comprising: determining an operationally beneficial number of address decoders to be activated in response to a valid input address, and configuring the comparison threshold such that a valid input address will activate a number of address decoders equal to the operationally beneficial number of address decoders to be activated. ### Claim 20 (depends on 19) A method according to claim 19, wherein the comparison compares the number of bits set to the first selectable state in the input address with the number of bits set to the first selectable state in each of the address decoder identifiers. ### Claim 21 (depends on 19) A method according to claim 19, wherein the operationally beneficial number is determined so as to allow maximum error free data recovery from the data memory. ### Claim 22 (depends on 21) A method according to, claim 21, wherein the operationally beneficial number is determined using a function of the form: w=f(h, Pc, D, d) where: w is the operationally beneficial number of address decoders to be activated; h is the probability of an arbitrary bit in the data memory being set to the first selectable state; D is the number of bits in each word line, and each word line has d bits set to the first selectable state; and Pc is the probability of a bit being correctly recovered from the data store. ### Claim 23 (depends on 22) A method according to claim 22, wherein the function is: h - w · w = ln ⁡ ( 1 - h ) ln ⁡ ( P c ) · W · D d · ( D - d ) . ### Claim 24 (depends on 19) A method according to claim 19, wherein the operationally beneficial number of address decoders to be activated is determined so as to allow maximum error free data recovery, while allowing some data to be recovered with errors. ### Claim 25 (depends on 24) A method according to claim 24, wherein the operationally beneficial number is determined using a function of the form: w=f(h, D, d) where: w is the operationally beneficial number of address decoders to be activated; h is the probability of an arbitrary bit in the data memory being set to the first selectable state; D is the number of bits in each word line, and each word line has d bits set to the first selectable state. ### Claim 26 (depends on 25) A method according to claim 25, wherein the function is: ( h - w - 1 ) w = - ( D - d ) · ln ⁢ ⁢ h . ### Claim 27 (depends on 19) A method according to claim 19, wherein the operationally beneficial number w is set so as to have a value no less than that given by the equation: ( h - w - 1 ) w = - ( D - d ) · ln ⁢ ⁢ h . and no more than that given by the equation: h - w · w = ln ⁡ ( 1 - h ) ln ⁡ ( P c ) · W · D d · ( D - d ) . ### Claim 28 (depends on 14) A computer-readable storage medium containing a computer program which, when executed by a computer, carries out the method of claim 14. ### Claim 29 A memory configuration for use in a computer system, the memory comprising: a plurality of address decoders each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states; a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select a predetermined one of the plurality of word lines; the address decoders comprising means to receive an input address having a predetermined number of bits and means to compare the identifier of an address decoder with the input address, and wherein the memory further comprises means to activate an address decoder if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier. ### Claim 30 A method for operating a memory for use in a computer system, the method comprising: allocating to each of a plurality of address decoders an identifier having a predetermined number of bits, each bit having first and second selectable states; and activating each of said address decoders to select a predetermined one of a plurality of word lines in a data memory having a plurality of word lines of predetermined length, wherein an input address having a predetermined number of bits is input to the address decoder, the identifier of an address decoder is compared with the input address and address decoders are activated if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier. ### Claim 31 A memory configuration for use in a computer system, the memory comprising: a plurality of address decoders, each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states; and a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select one of the plurality of word lines; the address decoders including means to receive an input address having a predetermined number of bits and means to compare the identifier of an address decoder with the input address; wherein the memory further includes means to activate an address decoder if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier; wherein the data memory comprises a plurality of single bit memories, such that each bit of each word line is stored in a single bit memory; and wherein the data memory comprises a data input line containing an equal number of bits to each of the plurality of word lines, the data input line being configured to receive input data containing a predetermined number of bits set to the first selectable state.