Hardware description language code generation from a state diagram
AssigneeThe MathWorks, Inc.
InventorsZhihong Zhao, Aditya Agrawal, Beth Cockerham, Vijay Raghavan
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Abstract
The present invention provides a state diagramming environment in a computing device that enables the conversion of a state diagram into a hardware description language. To achieve this conversion, the present invention generates an intermediate representation of the state diagram. The intermediate representation is checked against a set of predefined restrictions for compliance. The state diagramming environment converts the intermediate representation of the state diagram into a hardware description language, such as VHDL or Verilog.
Claims24
A computer-readable medium that stores instructions executable by at least one processor, the computer-readable medium comprising:
- one or more instructions for interacting with a state diagram in a state diagramming environment;
- one or more instructions for generating an intermediate representation of the state diagram based on information in the state diagram;
- one or more instructions for identifying one or more type casts associated with the intermediate representation;
- one or more instructions for transforming the intermediate representation of the state diagram into a lower-level representation of the state diagram;
- and
- one or more instructions for generating a hardware description language representation of the state diagram based on the lower-level representation.
A state diagram modeling system, comprising:
- a parser to identify syntactical components of a state diagram;
- an intermediate representation generator to generate an intermediate representation of the state diagram based on the identified syntactical components;
- a transformer to transform the intermediate representation of the state diagram into a lower-level representation of the state diagram;
- and
- a backend to generate and output a hardware description language representation of the state diagram, where the backend further comprises:
- a conformance checker to identify conformance of the intermediate representation with a set of predefined restrictions associated with generating the hardware description language representation,
- a type checker to ensure bit-true compatibility between the hardware description language representation and a simulation result of the state diagram,
- a second transformer to transform the lower-level representation of the state diagram into a hardware description language intermediate representation, and
- a code generator to generate the hardware description language representation based on the hardware description language intermediate representation.
A computing device-implemented method, comprising:
- interacting with a state diagram;
- generating an intermediate representation of the state diagram based on information included in the state diagram;
- identifying one or more type casts associated with the intermediate representation;
- transforming the intermediate representation of the state diagram into a lower-level representation of the state diagram;
- and
- generating a hardware description language representation of the state diagram based on the lower-level representation.
A computing device-implemented method, comprising:
- interacting with a graphical state diagram in a graphical state diagramming environment, where the graphical state diagram includes syntax and semantics to generate code;
- generating an intermediate representation of the state diagram based on syntax and semantics of the graphical state diagram;
- identifying one or more type casts associated with the intermediate representation;
- mapping the semantics of the intermediate representation to semantics of a hardware description language;
- and
- generating code in the hardware description language based on the mapping of the semantics of the intermediate representation to semantics of the hardware description language.
Dependencies are inferred from the claim text.