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US 7,502,275 B2Granted
Semiconductor memory device
AssigneeRenesas Technology Corp.
InventorsKoji Nii, Shigeki Obayashi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
Life of this patent
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Abstract
Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
Claims10
A semiconductor device comprising:
- a plurality of memory cells arranged in rows and columns;
- a plurality of bit lines, arranged corresponding to memory cell columns, each connected to the memory cells on a corresponding column;
- a plurality of cell power supply lines, arranged corresponding to the memory cell columns, each for supplying a first power supply voltage to the memory cells on a corresponding column;
- and
- a plurality of write assist circuits, arranged corresponding to the memory cell columns, each for selectively shutting off supply of the first power supply voltage to a corresponding cell power supply line and to set the corresponding cell power supply line to a floating state according at least to a voltage on the bit line in a corresponding column in a data write operation.
2 more elements
A semiconductor device comprising:
- a plurality of memory cells arranged in rows and columns;
- a plurality of hit lines, arranged corresponding to memory cell columns, each connected to the memory cells on a corresponding column;
- a plurality of cell power supply lines, arranged corresponding to the memory cell columns, each for supplying a first power supply voltage to the memory cells on a corresponding column;
- and
- a plurality of write assist circuits, arranged corresponding to the memory cell columns, each for selectively shutting off supply of the first power supply vo1tage to a corresponding cell power supply line according at least to a voltage on the bit line in a corresponding column in a data write operation, wherein
- each of the write assist circuits further includes:
- a one-shot pulse generating circuit for producing a one shot pulse signal in response to a potential change of a corresponding bit line on the corresponding column, and
- a potential adjusting circuit for driving the potential of the corresponding cell power supply line from the first power supply voltage toward a second power supply voltage in response to the one-shot pulse signal.
5 more elements
A semiconductor device comprising:
- a plurality of memory cells arranged in rows and columns;
- a plurality of bit lines, arranged corresponding to memory cell columns, each connected to the memory cells on a corresponding column;
- a plurality of first cell power supply lines, arranged corresponding to the memory cell columns;
- a plurality of second cell power supply lines, arranged corresponding to the memory cell columns;
- and
- a plurality of write assist circuits, arranged corresponding to the memory cell columns,
- wherein each of the memory cells includes two P-channel transistors, two N-channel transistors, and two access transistors connected to the pair of bit lines,
- wherein each of the first cell power supply lines connected to a first supply node via each of first and second transistors in parallel to each other, each of the first cell power supply lines supplies a first power supply voltage to the P-channel MOS transistors of the memory cells on a corresponding column,
- wherein each of the second transistors has a gate connected to each of the first cell power supply lines,
- wherein each of the second cell power supply lines supplies a second power supply voltage source lower than the first power supply voltage to the N-channel MOS transistors of the memory cells on a corresponding column, and
- wherein each of the write assist circuits selectively turns off each of the first transistors connected to a corresponding cell power supply line according at least to a voltage on the bit line in a corresponding column in a data write operation.
8 more elements
A semiconductor device comprising:
- a plurality of memory cells arranged in rows and columns;
- a plurality of bit lines, arranged corresponding to memory cell columns, each connected to the memory cells on a corresponding column;
- a plurality of first cell power supply lines, arranged corresponding to the memory cell columns;
- a plurality of second cell power supply lines, arranged corresponding to the memory cell columns;
- and
- a plurality of write assist circuits, arranged corresponding to the memory cell columns,
- wherein each of the memory cells includes two P-channel transistors, two N-channel transistors, and two access transistors connected to the pair of bit lines,
- wherein each of the first cell power supply lines is connected to a first supply node of a first power supply voltage via each of first transistors and connected to a second supply node of a second power supply voltage lower than the first power supply voltage via each of second transistors,
- wherein each of the second cell power supply lines supplies a third power supply voltage lower than the second power supply voltage to the N-channel MOS transistors of the memory cells on a corresponding column, and
- wherein each of the write assist circuits selectively turns off each of the first transistors and turns on each of the second transistors connected to a corresponding cell power supply line according at least to a voltage on the bit line in a corresponding column in a data write operation.
7 more elements
Dependencies are inferred from the claim text.