Integrated circuit having memory array including row redundancy, and method of programming, controlling and/or operating same

A method of programming a redundant row of memory cells into an integrated circuit device, the integrated circuit device comprising (a) a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns including (i) a plurality of normal rows of memory cells which are associated with and selectable via normal row addresses and (ii) a redundant row of memory cells which is associated with and selectable via a redundant row address, (b) address decoder circuitry to generate decoded row address data in response to an applied row address, and (c) a redundancy memory, the method comprising:

• determining the redundant row address based on detecting one or more bit failures or anticipated bit failures of memory cells of a row of memory cells of the plurality of normal rows of memory cells;
• generating a decoded redundant row address data by applying the redundant row address to the address decoder circuitry, wherein the decoded redundant row address data corresponds to the redundant row address;
• generating a redundancy program signal;
• and
• storing the decoded redundant row address data in the redundancy memory in response to the redundancy program signal.

A method of operating an integrated circuit device comprising (a) a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns including (i) a plurality of normal rows of memory cells which are associated with and selectable via normal row addresses and (ii) a redundant row of memory cells which is associated with and selectable via a redundant row address, (b) address decoder circuitry to generate decoded row address data in response to an applied row address, (c) a redundancy memory to store decoded redundant row address data, (d) normal word line drivers and (a) redundant word line drivers, the method comprising:

• generating the decoded row address data in response to an applied row address;
• responsively enabling (i) at least one of the normal rows of memory cells or (ii) the redundant row of memory cells using the decoded row address data;
• and
• determining, during operation, whether the decoded row address data corresponds to the decoded redundant row address data stored in the redundancy memory, and, in response thereto, enabling the redundant word line drivers and disabling the normal word line drivers.