Method and device for wafer backside alignment overlay accuracy

A method for determining an overlay accuracy of a backside alignment process, the method comprising:

• forming a thin oxide layer on a front-side of a semiconductor wafer;
• forming a conductive layer on the thin oxide layer;
• patterning an alignment mark and a test structure in the conductive layer;
• forming a thick oxide layer on the patterned conductive layer;
• flipping the semiconductor wafer over so that a backside of the wafer is facing up;
• etching through the semiconductor wafer from the backside to the front-side to perform a backside alignment process with the alignment mark;
• patterning and etching through the conductive layer after performing the backside alignment process;
• and
• measuring the test structure to determine the overlay accuracy of the backside alignment process.