US 7,492,632 B2Granted

Memory array having a programmable word length, and method of operating same

AssigneeInnovative Silicon ISi SA

InventorEric Carman

Life of this patent

Estimating the term…

Loading patent…

Abstract

A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array. In one aspect, write and/or read operations may be performed with respect to selected memory cells of a selected row of the memory array, while unselected memory cells of the selected row are undisturbed.

Claims31

Dependent claims

An integrated circuit device comprising:

a memory cell array including:
a plurality of word lines;
a plurality of source lines;
a plurality of bit lines;
and
a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes an electrically floating body transistor, wherein the electrically floating body transistor includes:
a first region coupled to an associated source line;
a second region coupled to an associated bit line;
a body region disposed between the first region and the second region, wherein the body region is electrically floating;
a gate disposed over the body region and coupled to an associated word line;
and
wherein each memory cell includes a plurality of data states, including:
(i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor;
and
(ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor;
first circuitry, coupled to each memory cell of a first row of memory cells, to perform a write operation with respect to memory cells of the first row of memory cells by concurrently applying:
(i) write control signals to a first group of memory cells of the first row of memory cells to write one of the plurality of data states in each memory cell of the first group, and
(ii) write de-select control signals to a second group of memory cells of the first row of memory cells to inhibit the write operation with respect thereto, and thereby inhibit writing any of the plurality of data states in the second group of memory cells during the write operation.

15 more elements

An Integrated circuit device comprising;

a semiconductor memory array including:
a plurality of word lines;
a plurality of source lines;
a plurality of bit lines;
and
a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes an electrically floating body transistor, wherein the electrically floating body transistor includes:
a first region coupled to an associated source line;
a second region coupled to an associated bit line;
a body region disposed between the first region and the second region, wherein the body region is electrically floating;
a gate disposed over the body region and coupled to an associated word line;
and
wherein each memory cell includes at least two data states, including:
(i) a first data state which is representative of a first charge in the body region of the associated electrically floating body transistor;
and
(ii) a second data state which is representative of a second charge in the body region of the associated electrically floating body transistor;
and
circuitry, coupled to each memory cell of a first row of memory cells, to perform a read operation with respect to memory cells of the first row of memory cells by concurrently applying:
(i) read control signals to a first group of memory cells of the first row of memory cells to read the data state of each memory cell of the first group of memory cells, and
(ii) read de-select control signals to a second group of memory cells of the first row of memory cells to inhibit the read operation with respect to the second group of memory cells of the first row of memory cells and thereby inhibit reading the data state of each memory cell of the second group of memory cells during the read operation.

16 more elements

An integrated circuit device comprising;

a semiconductor memory array, disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate, the semiconductor memory array, comprising:
a plurality of word lines;
a plurality of source lines;
a plurality of bit lines;
and
a plurality of dynamic random access memory cells disposed in or on the semiconductor region or layer and arranged in a matrix of rows and columns, each dynamic random access memory cell includes at least one transistor having:
a first region coupled to an associated source line;
a second region coupled to an associated bit line;
a body region disposed between the first region and the second region, wherein the body region is electrically floating;
a gate disposed over the body region and coupled to an associated word line;
and
wherein each memory cell includes at least two data states, including:
(i) a first data state which is representative of a first charge in the body region of the associated electrically floating body transistor;
and
(ii) a second data state which is representative of a second charge in the body region of the associated electrically floating body transistor;
first circuitry, coupled to each memory cell of a first row of memory cells, to perform a write operation with respect to memory cells of the first row of memory cells by concurrently applying:
(i) write control signals to a first group of memory cells of the first row of memory cells to write one of the plurality of data states in each memory cell of the first group, and
(ii) write de-select control signals to a second group of memory cells of the first row of memory cells to inhibit the write operation with respect thereto, and
thereby inhibit writing any of the plurality of data states in the second group of memory cells during the write operation;
and
second circuitry, coupled to each memory cell of the first row of memory cells, to perform a read operation with respect to memory cells of the first row of memory cells by concurrently applying:
(i) read control signals to the first group of memory cells of the first row of memory cells to read the data state of each memory cell of the first group of memory cells, and
(ii) read de-select control signals to the second group of memory cells of the first row of memory cells to inhibit the read operation with respect thereto, and thereby inhibit reading the data state of each memory cell of the second group of memory cells during the read operation.

20 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/724,552Filed 15 Mar 2007 · us provisional application
Priority: 7 Apr 2006
Published: US 2007/0285982 A113 Dec 2007
Granted: 17 Feb 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

G11C 7/1006
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data managing, e.g. manipulating data before…
G11C 11/404
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with one charge-transfer gate, e.g. MOS transistor, per cell
G11C 11/4087
Address circuits: address decoders, e.g. bit - or word line decoders; Multiple line decoders
G11C 11/4093
Read-write [R-W] circuits: input/output [I/O] data interface arrangements, e.g. data buffers