Designing an integrated circuit to improve yield using a variant design element

A method of designing an integrated circuit to improve yield when manufacturing the integrated circuit, the method comprising:

• obtaining a design element from a set of design elements used in designing integrated circuits;
• creating a variant design element based on the obtained design element, wherein a feature of the obtained design element is modified to create the variant design element;
• determining a yield to area ratio for the variant design element;
• if the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, retaining the variant design element to be used in designing the integrated circuit, wherein the design element is a memory unit, the set of design elements is a set of memory units, and the variant design element is a redundancy unit;
• and
• sorting the memory units in the set of memory units in order of largest macro area to smallest macro area.

A method of designing an integrated circuit to improve yield when manufacturing the integrated circuit, the method comprising:

• obtaining a design element from a set of design elements used in designing integrated circuits;
• creating a variant design element based on the obtained design element, wherein a feature of the obtained design element is modified to create the variant design element;
• determining a yield to area ratio for the variant design element;
• if the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, retaining the variant design element to be used in designing the integrated circuit, wherein the design element is an embedded memory unit, the set of design elements is a set of embedded memory units, and the variant design element is a memory type;
• and
• sorting the memory units in the set of memory units in order of largest macro area to smallest macro area.

A method of designing an integrated circuit to improve yield when manufacturing the integrated circuit, the method comprising:

• obtaining a design element from a set of design elements used in designing integrated circuits;
• creating a variant design element based on the obtained design element, wherein a feature of the obtained design element is modified to create the variant design element;
• determining a yield to area ratio for the variant design element;
• if the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, retaining the variant design element to be used in designing the integrated circuit, wherein the design element is a standard cell, the set of design elements is a library of standard cells, and the variant design element is a variant cell;
• and
• selecting one or more design modifications from a change list having a plurality of design modifications, wherein the feature of the standard is modified in accordance with the selected one or more design modifications.

A method of designing an integrated circuit to improve yield when manufacturing the integrated circuit, the method comprising:

• obtaining a design element from a set of design elements used in designing integrated circuits;
• creating a variant design element based on the obtained design element, wherein a feature of the obtained design element is modified to create the variant design element;
• determining a yield to area ratio for the variant design element;
• and
• if the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, retaining the variant design element to be used in designing the integrated circuit, wherein the design element is a gate-level net-list, the set of design elements is a set of gate-level net-lists, and the variant design element is a variant gate-level net-list, and wherein a feature of the obtained gate-level net-list is modified by:
• changing a router/placer configuration file;
• or
• changing router/placer/options switches.

A method of designing an integrated circuit to improve yield when manufacturing the integrated circuit, the method comprising:

• obtaining a design element from a set of design elements used in designing integrated circuits;
• creating a variant design element based on the obtained design element, wherein a feature of the obtained design element is modified to create the variant design element;
• determining a yield to area ratio for the variant design element;
• if the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, retaining the variant design element to be used in designing the integrated circuit;
• and
• determining post tape-out modifications, wherein determining post tape-out modifications comprises:
• determining existing failures models;
• determining modifications of layout attributes;
• determining yield impact of the determined modifications;
• generating a modified layout using the determined modifications;
• predicting yield of the modified layout;
• and
• verifying the modified layout.

A system for designing an integrated circuit to improve yield when manufacturing the integrated circuit, the system comprising:

• a design element obtained from a set of design elements used in designing integrated circuits;
• a variant design element created based on the obtained design element, wherein a feature of the obtained design element is modified to create the variant design element;
• a processor configured to:
• determine a yield to area ratio for the variant design element, and
• if the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, retain the variant design element to be used in designing the integrated circuit;
• and
• one or more existing failure models, wherein the one or more existing failure models are obtained by:
• extracting attributes from a product design layout;
• designing failure model test chips based on the extracted attributes and possible modifications of the extracted attributes;
• manufacturing the designed failure model test chips;
• and
• testing and analyzing the manufactured failure model test chips to determine failures rates.

A computer readable storage medium containing computer executable instructions for causing a computer to aid in the design of an integrated circuit to improve yield when manufacturing the integrated circuit, comprising instructions for:

• obtaining a design element from a set of design elements used in designing integrated circuits;
• creating a variant design element based on the obtained design element, wherein a feature of the obtained design element is modified to create the variant design element;
• determining a yield to area ratio for the variant design element, wherein the area in the yield to area ratio corresponds to the area of the entire variant design element;
• if the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, retaining the variant design element to be used in designing the integrated circuit, wherein the design element is a standard cell, the set of design elements is a library of standard cells, and the variant design element is a variant cell;
• and
• selecting one or more design modifications from a change list having a plurality of design modifications, wherein the feature of the standard is modified in accordance with the selected one or more design modifications.