Shift register, scan driving circuit and display apparatus having the same

A shift register having a plurality of stages to generate a plurality of output signals in sequence, each of the stages comprising:

• a driving circuit configured to generate a first output signal in response to a first clock signal or a second clock signal having a phase different from the first clock signal;
• a charging circuit configured to charge an electric charge in response to a scan start signal or a second output signal of an adjacent previous stage;
• a discharging circuit configured to discharge the electric charge in response to a third output signal of an adjacent next stage;
• a hold controlling circuit configured to generate a hold control signal in response to the first or the second clock signal applied to the driving circuit;
• and
• a holding circuit configured to maintain the first output signal within a first voltage in response to the hold control signal, the holding circuit comprising a first hold transistor that maintains the first output signal within the first voltage in response to the first clock signal.

A shift register having a plurality of stages to generate a plurality of output signals in sequence, each of the stages comprising:

• a driving circuit configured to generate a first output signal in response to one of a plurality of clock signals;
• a charging circuit configured to charge an electric charge in response to a scan start signal or a second output signal of an adjacent previous stage;
• a discharging circuit configured to discharge the electric charge in response to a third output signal of an adjacent next stage;
• and
• a holding circuit configured to maintain the first output signal within a first voltage when the first output signal is in an inactive state, the holding circuit comprising a first hold transistor that maintains the first output signal within the first voltage in response to the first clock signal.

A shift register having a plurality of stages to generate a plurality of output signals in sequence, each of the stages comprising:

• a charging circuit configured to charge an electric charge in response to a scan start signal or a second output signal of an adjacent previous stage;
• a driving circuit configured to pull up a first output signal of a present stage in response to the electric charge and one of a first clock signal and a second clock signal having a phase different from the first clock signal, the driving circuit configured to pull down the first output signal in response to a third output signal of an adjacent next stage;
• a discharging circuit configured to discharge the electric charge in response to the third output signal;
• a hold controlling circuit configured to output a hold control signal in response to the first or the second clock signal applied to the driving circuit, the hold controlling circuit comprising a first hold transistor including a first electrode that receives the first clock signal, a control electrode that is electrically connected to the first electrode of the first hold transistor, and a second electrode;
• and
• a holding circuit configured to maintain the first output signal within a first voltage in response to the hold control signal to prevent a floating of the driving circuit.

A scan driving circuit including a plurality of stages to generate a plurality of output signals in sequence, each of the stages comprising:

• a charging circuit configured to charge an electric charge in response to a scan start signal or a second output signal of an adjacent previous stage;
• a driving circuit configured to pull up a first output signal of a present stage in response to the electric charge and one of a first clock signal and a second clock signal having a phase different from the first clock signal, the driving circuit configured to pull down the first output signal in response to a third output signal of an adjacent next stage;
• a discharging circuit configured to discharge the electric charge in response to the third output signal;
• and
• a holding circuit configured to maintain the first output signal within a first voltage in response to the first or the second clock signal applied to the driving circuit to prevent a floating of the driving circuit, the holding circuit comprising a first hold transistor including a first electrode that is electrically connected to the control electrode of the driving transistor, a second electrode that is electrically connected to the second electrode of the driving transistor, and a control electrode receiving the first clock signal.

A display apparatus including a display cell array circuit that is disposed on a substrate to have a plurality of data lines and a plurality of scan lines and a shift register that includes a plurality of stages to generate a plurality of output signals in sequence, each of the stages comprising:

• a driving circuit configured to generate a first output signal of a present stage in response to a first clock signal or a second clock signal having a phase different from the first clock signal;
• a charging circuit configured to charge an electric charge in response to the scan start signal or the second output signal;
• a discharging circuit configured to discharge the electric charge charged in the charging circuit in response to a third output signal of an adjacent next stage;
• and
• a holding circuit configured to maintain the first output signal of the present stage within a first voltage, the holding circuit comprising a first hold transistor that maintains the first output signal within the first voltage in response to the first clock signal.

A display apparatus comprising:

• a display cell array circuit disposed on a substrate to include a plurality of data lines and a plurality of scan lines;
• a first scan driving circuit including a shift register that has a plurality of stages to generate a plurality of output signals corresponding to the stages to the scan lines in sequence, a first stage receiving a scan staff signal, each of the output terminals being electrically connected to each of first ends of the scan lines;
• and
• a second scan driving circuit electrically connected to second ends of the scan lines to discharge electric charges formed by the output signals that are applied to the scan lines, the second scan driving circuit including a first hold transistor comprising:
• a first electrode electrically connected to a second end of the scan lines which corresponds to a present stage;
• a second electrode which receives a second voltage;
• and
• a control electrode electrically connected to a second end of the scan lines which corresponds to an adjacent next stage.