US 7,480,886 B2 · VLSI timing optimization with interleaved buffer insertion and wire sizing stages

Abstract

The invention relates to layout of circuit components, including determining the interconnections, buffers, or path nets between circuit blocks or circuit components and input/output bonding pads. This is accomplished by a method and program product that optimizes timing comprising. Wiring layout and buffer insertion is accomplished by setting all wires in the design to an initial best possible value, inserting buffers in longest nets of wires of the design, and degrading the resulting nets. This is accomplished by a wire sizing routine which takes the nets and degrades them accordingly. This degrading is done through a combination of one or more of knocking the wires down to lower levels and reducing their thickness. The amount of degradation is dependent on the final slack.

Claims8

Dependent claims

A method of wire layout in an electronic circuit design to optimize timing comprising:

a) setting all wires in the design to a highest metal layer and widest wire;
b) inserting buffers in longest nets of wires in the design, wherein said longest nets of wires have overall lengths, as a sum of all segments for multi-fanout nets, at least twice as long as a best wire that can drive a normal load under nominal conditions;
and
c) degrading nets based on a wire delay to slack ratio, and
d) repeating steps b) and c) for optimizing slack.

2 more elements

Dependencies are inferred from the claim text.

VLSI timing optimization with interleaved buffer insertion and wire sizing stages

Life of this patent

VLSI timing optimization with interleaved buffer insertion and wire sizing stages

Life of this patent

Abstract

Claims8