Method and computer program for static timing analysis with delay de-rating and clock conservatism reduction

A computer program product for optimizing register transfer level code for an integrated circuit design comprising a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform steps of:

• receiving as input minimum and maximum stage delays for two corners of an integrated circuit design;
• calculating path slack for a setup timing check from the minimum and maximum stage delays as a function of net clock cycle interval T_clk, launch path delay T_LP, capture path delay T_CP, data path delay T_DP, and a first delay de-rating factor Y1;
• calculating path slack for a hold timing check from the minimum and maximum stage delays as a function of the launch path delay T_LP, the capture path delay T_CP, the data path delay T_DP, and a second delay de-rating factor Y2;
• and
• generating as output the path slack calculated for the setup timing check and for the hold timing check.