Method and system for layout versus schematic validation of integrated circuit designs
AssigneeLSI Logic Corporation
InventorsAlan Lee Holesovsky, Viswanathan Lakshmanan, Brent Wray Acott
Life of this patent
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Abstract
A method and system for validating selected layers of an integrated circuit design. A rundeck is edited to include IC layers and device structures of interest that may require validation. In some embodiments the IC layer of interest may include only metal. A layout versus schematic (LVS) comparison is performed using the edited rundeck and an error report is generated.
Claims10
A method for performing a trimmed verification analysis in an integrated circuit (IC), the method comprising:
- selecting IC layer definitions of interest and additional device structure descriptions of interest;
- creating a rundeck including the selections;
- analyzing the created rundeck, wherein the analyzing comprises:
- selecting a geometric design system file from the created rundeck;
- extracting a layout netlist from the geometric design system file;
- selecting a schematic netlist from the created rundeck;
- and
- comparing the schematic netlist with the layout netlist;
- and
- generating an error report based on a result of the analysis.
A computer program product comprising a computer usable medium including computer usable program instructions for performing a trimmed verification analysis, the instructions when executed by a processor performing actions comprising:
- selecting IC layer definitions of interest and additional device structure descriptions of interest;
- creating a rundeck including the selections;
- analyzing the created rundeck, wherein the analyzing comprises:
- selecting a geometric design system file from the created rundeck;
- extracting a layout netlist from the geometric design system file;
- selecting a schematic netlist from the rundeck;
- and
- comparing the schematic netlist with the layout netlist;
- and
- generating, by performing a layout versus schematic comparison, an error report based on a result of the analysis.
A system for performing a verification analysis, the system comprising:
- a storage device connected to a bus, the storage device comprising a computer readable storage medium including instructions;
- and
- a processor, wherein the processor executes the instructions that select IC layer definitions of interest and additional device structure description of interest;
- create a rundeck including the selections, based on a type of verification analysis to be performed;
- analyze the created rundeck by performing a layout versus schematic comparison, wherein the analyzing comprises:
- selecting a geometric design system file from the created rundeck;
- extracting a layout netlist from the geometric design system file;
- selecting a schematic netlist from the rundeck;
- and
- comparing the schematic netlist with the layout netlist;
- and
- generate an error report based on a result of the analysis.
Dependencies are inferred from the claim text.