US 7,480,875 B2 · Method of designing a semiconductor integrated circuit

Abstract

In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while considering dynamically a cell activation rate. In other words, in estimating a power-supply capacitance inserted to suppress a voltage fluctuation of the power supply, an areal demerit can be reduced by reducing a necessary capacitance component as a whole while considering a cell activation rate in the circuit or by selecting the capacitance required to supplement only temporal portions whose power-supply fluctuation is wide after the estimation of a cell operating timing. Also, the process can be conducted in a short time at the early stage of design by using a wiring load model at the time of capacitance estimate.

Claims6

Dependent claims

A method of designing a semiconductor integrated circuit, comprising the steps of:

calculating a total capacitance required to optimize a voltage drop from circuit information, while considering whether or not respective cells in an object circuit are in an active status;
reading a maximum allowable current value of the semiconductor integrated circuit from net list information in the circuit information;
generating a load model from the net list information in the circuit information, and then calculating a cell operating time based on the load model;
calculating each cell power consumption based on the load model;
and
calculating dynamic power consumption information based on the cell operating time and the cell power consumption;
wherein the step of calculating the total capacitance includes:
converting the dynamic power consumption information into dynamic current information;
and
calculating a capacitance value required to restrain the dynamic current within the maximum allowable current value.

7 more elements

Dependencies are inferred from the claim text.

Method of designing a semiconductor integrated circuit

Life of this patent

Method of designing a semiconductor integrated circuit

Life of this patent

Abstract

Claims6