Method for eliminating hold error in scan chain

A method for eliminating a hold error from a scan chain configured by connecting a plurality of data holding circuits with wiring, the method comprising:

• determining a hold error value and a hold margin value for each virtual wiring connecting the data holding circuits;
• determining a combination of virtual wirings so that the hold error is reduced;
• reordering the data holding circuits based on the determined combination;
• and
• inserting one or more delay elements based on the determined number of delay elements between the scan-out terminal and a connection point of the further data holding circuit.

A method for eliminating a hold error from a scan chain configured by connecting a plurality of data holding circuits, wherein each data holding circuit has a scan-out terminal connected to a delay element and a further data holding circuit, the method comprising:

• determining a hold error value in the scan chain;
• determining the number of delay elements necessary to eliminate the hold error based on the hold error value;
• and
• inserting one or more delay elements based on the determined number of delay elements between the scan-out terminal and a connection point of the further data holding circuit.

A method for eliminating a hold error from a scan chain configured by connecting a plurality of data holding circuits, wherein each data holding circuit has a scan-out terminal connected to a delay element and a further data holding circuit, the method comprising:

• determining a position of a hold error in the scan chain and a hold error value;
• determining the number of delay elements necessary to eliminate the hold error based on the hold error value;
• and
• determining the number of delay elements necessary to eliminate the hold error based on the hold error value;
• and
• inserting one or more delay elements according to the determined number of delay elements between the scan-out terminal and a connection point of the further data holding circuit.

A method for eliminating a hold error from a scan chain configured by connecting a plurality of data holding circuits with wiring, wherein each data holding circuit has a scan-out terminal connected to a delay element by wiring and a further data holding circuit, the method comprising:

• determining a position of a hold error in the scan chain, hold error value, and a hold margin value for each virtual wiring connecting the data holding circuits;
• determining a combination of virtual wirings so that the hold error is reduced;
• reordering the data holding circuits based on the determined combination;
• re-determining the position of the hold error in the scan chain and the hold error value after said reordering;
• selectively inserting a delay element between the data holding circuits to eliminate the hold error from the scan chain after the reordering.

A method for eliminating a hold error from a scan chain comprised of a plurality of data holding circuits with wiring, the method comprising:

• identifying the hold error in the scan chain;
• determining a virtual wiring so that the hold error is maximally reduced;
• reordering the data holding circuits based on the determined virtual wiring,
• determining a remaining hold error in the scan chain;
• determining a number of delay elements corresponding to the remaining hold error;
• inserting the determined number of delay elements between the data holding circuits.