US 7,480,841 B2 · Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit

Abstract

A semiconductor integrated circuit includes a circuit under test coupled to the logic circuit to receive a plurality internal test signals and a delay time measurement terminal from which a delay time measurement signal is output. The delay time measurement signal is turned in accordance with a transition of one of the internal test signal. The semiconductor integrated circuit further includes a current generator coupled to the delay time measurement terminal, and still further includes a plurality of delay time measurement transistors coupled to the delay time measurement terminal. The delay time measurement transistors have a plurality of control electrodes coupled to the logic circuit to receive the internal test signals. Alternatively, the semiconductor integrated circuit may include an input switching circuit coupled between the logic circuit and the CUT and a pseudo test terminal coupled to the CUT and the logic circuit.

Claims12

Dependent claims

A semiconductor integrated circuit, operable normal operational mode and a test mode, comprising:

a plurality of external input terminals which receives a plurality of external signals;
a logic circuit coupled to the external input terminals, wherein the logic circuit outputs a plurality of internal input signals based on the external signals;
a circuit under test (CUT) coupled to the logic circuit to receive the internal input signals, wherein the CUT generates an internal output signal for the logic circuit when the semiconductor integrated circuit operates in the normal operational mode;
an input switching circuit coupled between the logic circuit and the CUT, wherein the input switching circuit prohibits the CUT from receiving the internal input signals when the semiconductor integrated circuit operates in the test mode;
a pseudo test terminal coupled to the CUT and the logic circuit, wherein a pseudo test signal is input to the logic circuit through the pseudo test terminal when the CUT is prohibited from receiving the internal input signals.

2 more elements

A semiconductor integrated circuit, operable a normal operational mode and a test mode, comprising:

a plurality of external input terminals which receives a plurality of external signals;
a logic circuit coupled to the external input terminals, wherein the logic circuit outputs a plurality of internal input signals based on the external signals, the internal signals including a data input signal;
a circuit under test (CUT) coupled to the logic circuit to receive the internal input signals, wherein the CUT generates an internal output signal for the logic circuit when the semiconductor integrated circuit operates in the normal operational mode;
an input switching circuit coupled between the logic circuit and the CUT, wherein the input switching circuit prohibits the CUT from receiving the internal input signals when the semiconductor integrated circuit operates in the test mode;
a pseudo test signal generating circuit coupled to the logic circuit to receive the data input signal, wherein the pseudo test signal generating circuit provides a pseudo test signal to the logic circuit based on the data input signal, when the CUT is prohibited from receiving the internal input signals.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit

Life of this patent

Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit

Life of this patent

Abstract

Claims12