Back to results
US 7,480,838 B1Granted
Method, system and apparatus for detecting and recovering from timing errors
AssigneeIntel Corporation
InventorsChris Wilkerson, Shih-Lien L. Lu, Edward Grochowski, Murali Annavaram
Life of this patent
Estimating the term…
Abstract
Methods and systems to facilitate an efficient circuit for detecting internal timing errors for integrated devices, including a hierarchy of reporting the detection of the timing error from a circuit level to a functional unit block (FUB) level up to a global detection, and a reorder buffer (ROB) for storing a result for timing error recovery until the timing can be verified to be error free.
Claims10
An apparatus for timing error detection comprising:
- a timing error detection circuit to generate a timing error detection zone, and to compare a first signal and a second signal during the timing error detection zone;
- a logic circuit to prevent all computed results from being written to architectural state until the results can be verified to be free of timing failures upon detection of a timing error by storing the results in a reorder buffer (ROB) until the timing is verified;
- a feedback controller to decrease an operating frequency or increase an operating voltage upon detection of the timing error;
- and
- a fetch logic unit to re-execute a failed instruction that results from detection of the timing error with a decreased operating frequency or increased operating voltage.
2 more elements
A system comprising:
- a dynamic random access memory to receive memory requests;
- at least one processor, to generate memory requests to the DRAM;
- the processor with:
- a timing error detection circuit to generate a timing error detection zone, and to compare a first signal and a second signal during the timing error detection zone;
- and
- a logic circuit to prevent all computed results from being written to architectural state until the results can be verified to be free of timing failures upon detection of a timing error by storing the results in a reorder buffer (ROB) until the timing is verified;
- a feedback controller to decrease an operating frequency or increase an operating voltage upon detection of the timing error;
- and
- a fetch logic unit to re-execute a failed instruction that results from detection of the timing error with a decreased operating frequency or increased operating voltage.
6 more elements
Dependencies are inferred from the claim text.