Centralized error signaling and logging
AssigneeIntel Corporation
InventorsSuresh Chemudupati, Victor T. Lau, Bruno DiPlacido, Eric J. DeHaemer
Life of this patent
Estimating the term…
Abstract
A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit operable to receive the synchronized error requests from the one or more error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.
Claims19
An error handling device, comprising:
- a plurality of error receiving units, each operable to receive error requests directly from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers;
- and
- an arbiter unit operable to receive the synchronized error requests directly from each of the plurality of error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.
A method, comprising:
- receiving error requests directly from each of a plurality of layers in a protocols;
- synchronizing the received error requests to a common clock domain for all of the plurality of layers in the protocol;
- and
- encoding the error requests onto on a common error interconnect;
- and
- routing the encoded error requests across the interconnect to configuration space.
A system, comprising:
- an error request interconnect;
- a common error interconnect;
- a plurality of error receiving units coupled to the error request interconnect, each operable to:
- receive all error requests from a given layer in a PCI Express protocol;
- synchronize the received error requests to a common clock domain for all layers;
- and
- send the synchronized requests across the error request interconnect;
- and
- an arbiter unit, coupled to the error request interconnect and the common error interconnect, operable to:
- receive the synchronized error requests on the error request interconnect from all of the plurality of error receiving units;
- encode the error requests onto the common error interconnect;
- and
- route the encoded error requests across the common error interconnect to appropriate configuration space.
Dependencies are inferred from the claim text.