Controller communications over an always-on controller interconnect

A controller interconnect structure in a disk array comprising:

• a plurality of controllers;
• a plurality of communications buses operatively coupling the plurality of controllers to one another, each communications bus partitioned into a first half and a second half;
• a first interconnect to which each of the plurality of controllers is coupled, the first interconnect conveying the first half of the plurality of communications buses;
• and
• a second interconnect to which each of the plurality of controllers is coupled, the second interconnect conveying the second half of the plurality of communications buses.

A processor-readable medium comprising processor-executable instructions configured for:

• determining a destination controller pair for a data packet based on a host address for the data packet and an array mapping of the host address to an array address;
• initially sending the data packet over a controller loop toward the destination controller pair in a first direction determined by a data header and a routing instruction;
• detecting a failure in the controller loop;
• rerouting the data packet in a second direction toward the destination controller pair;
• based on the failure, reprogramming a routing register with new routing information;
• based on the new routing information, initially sending additional data packets in a direction over the controller loop that avoids the failure;
• sharing failure information with all controllers;
• and
• based on the failure information, reprogramming routing registers on each controller with new routing information.

A processor-readable medium comprising processor-executable instructions configured for:

• receiving at a first controller in a first controller level, data that is destined for a second level controller pair located in a second controller level;
• sending the data over a first level controller loop to a first level controller pair that corresponds to the second level controller pair;
• and
• further sending the data from the first level controller pair to the second level controller pair via a loop bus that couples the first controller level to the second controller level.

A processor-readable medium comprising processor-executable instructions configured for:

• receiving data at a first controller in a first controller level;
• sending the data from the first controller to a second level controller pair via a loop bus that couples the first controller level to a second controller level;
• and
• further sending the data over a second level controller loop to a destination controller pair in the second controller level.

A method of routing data between controller pairs in a multi-controller disk array comprising:

• receiving at a first controller in a first controller level, data that is destined for a second level controller pair located in a second controller level;
• sending the data over a first level controller loop to a first level controller pair that corresponds to the second level controller pair;
• and
• further sending the data from the first level controller pair to the second level controller pair via a loop bus that couples the first controller level to the second controller level.

A method of routing data between controller pairs in a multi-controller disk array comprising:

• receiving data at a first controller in a first controller level;
• sending the data from the first controller to a second level controller pair via a loop bus that couples the first controller level to a second controller level;
• and
• further sending the data over a second level controller loop to a destination controller pair in the second controller level.