Microprocessor
AssigneeFujitsu Limited
InventorsRyosuke Kito, Masayuki Tsuji
Life of this patent
Estimating the term…
Abstract
A processor core adopts a pipeline processing method and has an interlock mechanism. A built-in accelerator executes a specific processing in place of the processor core. When a processing is executed by the built-in accelerator and there is no processing to be executed by the processor core, the interlock mechanism stops and restarts the pipeline processing in response to a start of processing and a processing completion of the built-in accelerator, respectively. A processing-completion waiting operation to the built-in accelerator is implemented by using the interlock mechanism, and thus useless power consumption of the processor core during the processing of the built-in accelerator can be easily reduced.
Claims9
A microprocessor comprising:
- a processor core performing pipeline processing method and having an interlock mechanism stopping and restarting the pipeline processing according to processing data so as to ensure justness of a result of the pipeline processing;
- and
- an assistance circuit that executes a specific processing in place of said processor core, wherein when the specific processing is executed by said assistance circuit and there is no pipeline processing to be executed by said processor core, said interlock mechanism stops and restarts the pipeline processing in response to a start and a completion, respectively, of the specific processing executed by said assistance circuit;
- wherein:
- said processor core has a normal mode and a low power consumption mode;
- and
- during the normal mode, when the specific processing is executed by said assistance circuit and there is no pipeline processing to be executed by said processor core, said processor core shifts to the low power consumption mode in response to the stop of the pipeline processing by said interlock mechanism through a completion waiting operation to said assistance circuit;
- and
- during the stop of the pipeline processing, said interlock mechanism restarts the pipeline processing in response to occurrence of an interrupt and stops the pipeline processing, again, after an interrupt processing by said processor core is completed.
Dependencies are inferred from the claim text.