Method and apparatus for managing power consumption relating to a differential serial communication link

An integrated circuit comprising:

• a differential serial communication circuit adapted to at least communicate clock recovery information in a data stream, wherein the differential serial communication circuit can form a link having a link width comprised of one or more lanes;
• dynamic link width control logic, operatively coupled to the differential serial communication circuit for managing power consumption corresponding to differential serial communication circuit, operative to change, during normal operating conditions, a number of active lanes of the differential serial communication link to change link width, based on a determined desired link width such that each active lane operates in a normal operational state of the differential serial communication link;
• a link width command register containing at least data representing a command that causes the dynamic link width control logic to change the link width to a size identified by a link width control register;
• the link width control register containing at least data representing a desired link width size;
• and
• wherein the dynamic link width control logic includes a state machine and wherein the integrated circuit includes logic operatively coupled to the dynamic link width control logic that is activated to cause the state machine to transition to a configuration state without transitioning to a detect state.

A system comprising:

• a first processor;
• a second processor that includes:
• a first differential serial communication circuit adapted to at least communicate clock recovery information in a data stream, wherein the differential serial communication circuit can form a link having a link width comprised of one or more lanes;
• and
• first dynamic link width control logic, operatively coupled to the differential serial communication circuit for managing power consumption corresponding to the first differential serial communication circuit, operative to change, during normal operating conditions, a number of active lanes of the differential serial communication link to change link width, based on a determined desired link width such that each active lane operates in a normal operational state of the differential serial communication link;
• memory;
• and
• a memory bridge circuit operatively coupled to the first processor through a bus and the memory through another bus, and including a second differential serial communication circuit adapted to at least communicate clock recovery information in a data stream, wherein the second differential serial communication circuit forms the link with the first differential serial communication circuit;
• and
• second dynamic link width control logic, operatively coupled to the second differential serial communication circuit for managing power consumption corresponding to the second differential serial communication circuit, operative to change, during normal operating conditions, a number of active lanes of the differential serial communication link to change link width, based on a determined desired link width such that each active lane operates in a normal operational state of the differential serial communication link and wherein the second processor includes logic operatively coupled to the dynamic link width control logic that is activated to cause a state machine to transition to a configuration state without transitioning to a detect state.