Methods and cores using existing PLD processors to emulate processors having different instruction sets and bus protocols

A method of using a soft processor in a Programmable Logic Device (PLD) to emulate a target processor, the soft processor supporting a first instruction set and conforming to a first bus protocol, the target processor supporting a target instruction set and conforming to a target bus protocol, the method comprising:

• configuring first programmable resources of the PLD to implement the soft processor;
• configuring second programmable resources of the PLD to implement a first bus interface unit, the first bus interface unit having a first port coupled to the soft processor and conforming to the first bus protocol, and further having a second port conforming to the target bus protocol;
• and
• executing in the soft processor an emulation program that emulates the target instruction set while executing instructions from the first instruction set, the emulation program interacting with the first bus interface unit via the first port,
• wherein the target instruction set is different from the first instruction set, and
• wherein the target bus protocol is different from the first bus protocol.

A processor core for a Programmable Logic Device (PLD), the processor core implementing a target processor supporting a target instruction set and conforming to a target bus protocol, the processor core comprising:

• an instantiation of a dedicated processor embedded in the PLD, wherein the dedicated processor supports a first instruction set and conforms to a first bus protocol, the dedicated processor having an address space;
• a first pre-defined functional block implementing a first bus interface unit, the first bus interface unit having a first port coupled to the dedicated processor and conforming to the first bus protocol, and further having a second port conforming to the target bus protocol;
• and
• an emulation program designated for storage in the address space of the dedicated processor, wherein the emulation program emulates the target instruction set while executing instructions from the first instruction set, the emulation program interacting with the first bus interface unit via the first port,
• wherein the target instruction set is different from the first instruction set, and
• wherein the target bus protocol is different from the first bus protocol.

A processor core for a Programmable Logic Device (PLD), the processor core implementing a target processor supporting a target instruction set and conforming to a target bus protocol, the processor core comprising:

• a first pre-defined functional block implementing a soft processor, wherein the soft processor supports a first instruction set and conforms to a first bus protocol, the soft processor having an address space;
• a second pre-defined functional block implementing a first bus interface unit, the first bus interface unit having a first port coupled to the soft processor and conforming to the first bus protocol, and further having a second port conforming to the target bus protocol;
• and
• an emulation program designated for storage in the address space of the soft processor, wherein the emulation program emulates the target instruction set while executing instructions from the first instruction set, the emulation program interacting with the first bus interface unit via the first port,
• wherein the target instruction set is different from the first instruction set, and
• wherein the target bus protocol is different from the first bus protocol.