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US 7,480,776 B2Granted
Circuits and methods for providing variable data I/O width for semiconductor memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsHan-gu Sohn, Hai-jeong Sohn, Sei-jin Kim, Woo-seop Jeong
Life of this patent
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Abstract
Circuits and methods for controlling data I/O operations in semiconductor memory devices to provide variable data I/O widths for read, write and active memory operations. Circuits and methods for selectively controlling a data width of a data I/O buffer “on the fly” to enable variable data I/O widths during memory access operations.
Claims23
A semiconductor memory device, comprising:
- an integrated circuit (IC) memory chip comprising an integrated memory circuit and a plurality of address pins, wherein the integrated memory circuit comprises:
- a memory cell array;
- a data buffer for processing data read from or written to the memory cell array;
- and
- a data width control circuit for selectively controlling a data width of the data buffer in response to one or more address bits of an external address signal applied to one or more address pins of the IC memory chip, wherein the data width control circuit comprises:
- a decoder for decoding the one or more address bits of the external address signal in response to a data access command to generate a first control signal;
- and
- a data buffer controller, responsive to the first control signal, to generate a second control signal for controlling the data width of the data buffer,
- wherein the decoder comprises:
- a switching circuit;
- and
- a logic circuit, wherein the switching circuit is responsive to the data access command in the form of a read command and a write command to pass the one or more address bits of the external address signal to the logic circuit and wherein the logic circuit processes the external address signal to generate the first control signal.
9 more elements
A semiconductor memory device, comprising:
- an integrated circuit (IC) memory chip comprising an integrated memory circuit and a plurality of address pins, wherein the integrated memory circuit comprises;
- a memory cell array;
- a data output buffer for outputting data read from the memory cell array;
- a data input buffer for inputting data to be written to the memory cell array;
- and
- a data width control circuit for selectively controlling a data width of the data output buffer or the data input buffer in response to one or more address bits of an external address signal applied to one or more of the address pins of the IC memory chip, wherein the data width control circuit comprises:
- a decoder which is activated in response to a read command signal or write command signal to decode the one or more address bits of the external address to generate a first control signal;
- a data input buffer controller which is activated in response to the write command signal to generate a second control signal for controlling the data width of the data input buffer based on the first control signal;
- and
- a data output buffer controller which is activated in response to the read command signal to generate a second control signal for controlling the data width of the data output buffer based on the first control signal,
- wherein the decoder comprises:
- a switching circuit;
- and
- a logic circuit, wherein the switching circuit is responsive to the read command signal and the write command signal to pass the one or more address bits of the external address signal to the logic circuit and wherein the logic circuit processes the external address signal to generate the first control signal.
11 more elements
An integrated circuit (IC) memory device, comprising:
- a memory data buffer;
- a data width control circuit for selectively varying a data width of the memory data buffer in response to one or more address bits of an external control signal applied to one or more address pins of the IC memory device;
- and
- a decoder for decoding the one or more address bits of the external address signal in response to a data access command to generate a first control signal;
- and
- a data buffer controller, responsive to the first control signal, to generate a second control signal for controlling the data width of the data buffer,
- wherein the decoder comprises:
- a switching circuit;
- and
- a logic circuit, wherein the switching circuit is responsive to a data access command in the form of a read command and a write command to pass the one or more address bits of the external address signal to the logic circuit and wherein the logic circuit processes the external address signal to generate the first control signal.
7 more elements
A memory system, comprising:
- a controller for generating data access command signals and address signals;
- and
- a semiconductor integrated circuit (IC) memory chip comprising:
- a plurality of address pins;
- a memory cell array;
- a data buffer for processing data read from or written to the memory cell array;
- a data width control circuit for selectively controlling a data wkith of the data buffer in response to one or more address bits of an external address signal applied to one or more of the address pins of the IC memory chip;
- and
- a decoder for decoding the one or more address bits of the external address signal in response to a data access command to generate a first control signal;
- and
- a data buffer controller, responsive to the first control signal, to generate a second control signal for controlling the data width of the data buffer,
- wherein the decoder comprises:
- a switching circuit;
- and
- a logic circuit, wherein the switching circuit is responsive to a data access command in the form of a read command and a write command to pass the one or more address bits of the external address signal to the logic circuit and wherein the logic circuit processes the external address signal to generate the first control signal.
12 more elements
A method for providing data I/O (input/output) width control in a semiconductor integrated circuit (IC) memory chip, comprising the steps of:
- generating a data width control signal in response to one or more address bits of an external address signal applied to one or more address pins of the IC memory chip;
- controlling a data width of a memory data buffer in response to the data width control signal to selectively vary a data width of the memory data buffer;
- and
- decoding the one or more address bits of the external address signal in response to a data access command to generate a first control signal;
- and
- generating, responsive to the first control signal, a second control signal for controlling the data width of the data buffer,
- wherein the step of decoding comprises:
- providing a switching operation;
- and
- performing a logic function, wherein the switching operation is responsive to the data access command in the form of a read command and a write command to pass the one or more address bits of the external address signal to the logic function and wherein the logic function processes the external address signal to generate the first control signal.
7 more elements
A semiconductor memory device, comprising:
- an integrated circuit (IC) memory chip comprising an integrated memory circuit and a plurality of address pins, wherein the integrated memory circuit comprises;
- a memory cell array;
- a data buffer for processing data read from or written to the memory cell array by a read command or write command;
- a data width control circuit for selectively controlling a data width of the data buffer in response to one or more address bits of an external address signal that is accompanied with the read command or write command, and which is applied to one or more of the address pins of the IC memory chip;
- and
- a decoder for decoding the one or more address bits of the external address signal in response to a data access command to generate a first control signal;
- and
- a data buffer controller, responsive to the first control signal, to generate a second control signal for controlling the data width of the data buffer,
- wherein the decoder comprises:
- a switching circuit;
- and
- a logic circuit, wherein the switching circuit is responsive to the a read command and the write command to pass the one or more address bits of the external address signal to the logic circuit and wherein the logic circuit processes the external address signal to generate the first control signal.
9 more elements
A semiconductor memory device, comprising:
- an integrated circuit (IC) memory chip comprising an integrated memory circuit and a plurality of address pins, wherein the integrated memory circuit comprises;
- a memory cell array;
- a data buffer for processing data read from or written to the memory cell array by a read command or write command;
- a data width control circuit for selectively controlling a data width of the data buffer in response to a one or more address bits of a redundant external address signal that is accompanied with the read command or write command, and which is applied to one or more of the address pins of the IC memory chip, and
- a decoder for decoding the one or more address bits of the external aidress signal in response to a data access command to generate a first control signal;
- and
- a data buffer controller, responsive to the first control signal, to generate a second control signal for controlling the data width of the data buffer,
- wherein the decoder comprises:
- a switching circuit;
- and
- a logic circuit, wherein the switching circuit is responsive to the read command and the write command to pass the one or more address bits of the redundant external address signal to the logic circuit and wherein the logic circuit processes the redundant external address signal to generate the first control signal.
8 more elements
Dependencies are inferred from the claim text.