US 7,480,771 B2 · Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged

Abstract

We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms.

Claims25

Dependent claims

A computer system comprising:

at least one processor;
a hierarchy of storage including a cache, wherein locations represented in the hierarchy are addressable by the processor;
and
a conditional multi-store mechanism that acquires ownership of a first cache line covering the target of a load-and-flag operation, wherein as long as the first cache line remains owned and contents thereof remain unmodified, the conditional multi-store mechanism allows results of plural successively executed conditional-store operations to become visible, individually and successively, in the storage.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

11/465,376Filed 17 Aug 2006 · us provisional application

Priority

17 Aug 2005

Published

US 2007/0043915 A122 Feb 2007

Granted

20 Jan 2009

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 12/0864
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: using…
G06F 9/3004
Arrangements for executing specific machine instructions: to perform operations on memory
G06F 9/30072
Arrangements for executing specific machine instructions: to perform conditional operations, e.g. using predicates or guards
G06F 9/30087
To perform miscellaneous control operations, e.g. NOP: synchronisation or serialisation instructions

Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged

Life of this patent

Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged

Life of this patent

Abstract

Claims25