Microprocessor with improved data stream prefetching

A computer program product for use with a computing device, the computer program product comprising:

• a computer usable storage medium, having computer readable program code embodied in said medium, for causing a microprocessor coupled to a system memory, said computer readable program code comprising:
• first program code for providing a load request signal, for requesting data be loaded from the system memory into the microprocessor in response to a load instruction, said load request signal including a load virtual page address;
• second program code for providing a prefetch request signal, for requesting a cache line be prefetched from the system memory into the microprocessor in response to a prefetch instruction, said prefetch request signal including a prefetch virtual page address;
• and
• third program code for providing a memory subsystem, comprising:
• a first translation look-aside buffer (TLB), coupled to said load request signal, for translating said load virtual page address into a load physical page address;
• a second TLB, coupled to said prefetch request signal, for translating said prefetch virtual page address into a prefetch physical page address;
• and
• a third TLB, coupled to said load request signal, for translating said load virtual page address into said load physical page address if said load virtual page address misses in said first TLB, and coupled to said prefetch request signal, for translating said prefetch virtual page address into said prefetch physical page address if said prefetch virtual page address misses in said second TLB.

A microprocessor coupled to a system memory, the microprocessor comprising:

• a load unit, for generating a load request to load data from the system memory into the microprocessor in response to a load instruction, said load request including a load virtual page address;
• N stream prefetch engines, for generating N respective prefetch requests to prefetch a cache line into the microprocessor from N respective data streams in the system memory, said N respective data streams specified by N respective stream prefetch instructions, said N respective prefetch requests each including a prefetch virtual page address;
• and
• a memory subsystem, comprising:
• a load/store translation look-aside buffer (TLB), coupled to translate said load virtual page address into a load physical page address;
• and
• N prefetch TLBs, coupled to translate said N respective prefetch virtual page addresses into N respective prefetch physical page addresses;
• wherein said N is greater than 1.

A computer program product for use with a computing device, the computer program product comprising:

• a computer usable storage medium, having computer readable program code embodied in said medium, for causing a microprocessor coupled to a system memory, said computer readable program code comprising:
• first program code for providing a load unit, for generating a load request to load data from the system memory into the microprocessor in response to a load instruction, said load request including a load virtual page address;
• second program code for providing N stream prefetch engines, for generating N respective prefetch requests to prefetch a cache line into the microprocessor from N respective data streams in the system memory, said N respective data streams specified by N respective stream prefetch instructions, said N respective prefetch requests each including a prefetch virtual page address;
• and
• third program code for providing a memory subsystem, comprising:
• a load/store translation look-aside buffer (TLB), coupled to translate said load virtual page address into a load physical page address;
• and
• N prefetch TLBs, coupled to translate said N respective prefetch virtual page addresses into N respective prefetch physical page addresses;
• wherein said N is greater than 1.